Intel PENTIUM P6000 - DATASHEET 2010 - Page 5

Datasheet 5
6.10 Error and Thermal Protection .............................................................................. 77
6.11 Power Sequencing ............................................................................................. 78
6.12 Processor Power Signals ..................................................................................... 79
6.13 Ground and NCTF .............................................................................................. 81
6.14 Processor Internal Pull Up/Pull Down.................................................................... 81
7 Electrical Specifications........................................................................................... 83
7.1 Power and Ground Pins ...................................................................................... 83
7.2 Decoupling Guidelines........................................................................................ 83
7.2.1 Voltage Rail Decoupling........................................................................... 83
7.3 Processor Clocking (BCLK, BCLK#) ...................................................................... 83
7.3.1 PLL Power Supply ................................................................................... 84
7.4 Voltage Identification (VID) ................................................................................ 84
7.5 Reserved or Unused Signals................................................................................ 88
7.6 Signal Groups ................................................................................................... 88
7.7 Test Access Port (TAP) Connection....................................................................... 91
7.8 Absolute Maximum and Minimum Ratings ............................................................. 92
7.9 Storage Conditions Specifications ........................................................................ 92
7.10 DC Specifications............................................................................................... 93
7.10.1 Voltage and Current Specifications............................................................ 94
7.11 Platform Environmental Control Interface (PECI) DC Specifications......................... 101
7.11.1 DC Characteristics ................................................................................ 101
7.11.2 Input Device Hysteresis......................................................................... 102
8 Processor Pin and Signal Information.................................................................... 103
8.1 Processor Pin Assignments................................................................................ 103
8.2 Package Mechanical Information........................................................................ 177
Figures
Figure 1-1 Intel® Pentium® P6000 and U5000 Mobile Processor Series on the Calpella
Platform..................................................................................................9
Figure 2-2 Intel Flex Memory Technology Operation ................................................... 21
Figure 2-3 Dual-Channel Symmetric (Interleaved) and Dual-Channel
Asymmetric Modes ................................................................................. 22
Figure 2-4 PCI Express Layering Diagram ................................................................. 24
Figure 2-5 Packet Flow through the Layers ................................................................ 25
Figure 2-6 PCI Express Related Register Structures in the Processor ............................. 26
Figure 2-7 Integrated Graphics Controller Unit Block Diagram...................................... 28
Figure 2-8 Processor Display Block Diagram .............................................................. 31
Figure 4-9 Idle Power Management Breakdown of the Processor Cores.......................... 40
Figure 4-10 Thread and Core C-State Entry and Exit .................................................... 40
Figure 4-11 Package C-State Entry and Exit ................................................................ 45
Figure 5-12 Frequency and Voltage Ordering............................................................... 57
Figure 7-13 Active V
CC
and I
CC
Loadline (PSI# Asserted) .............................................. 95
Figure 7-14 Active V
CC
and I
CC
Loadline (PSI# Not Asserted) ........................................ 95
Figure 7-15 VAXG/IAXG Static and Ripple Voltage Regulation ........................................ 97
Figure 7-16 Input Device Hysteresis......................................................................... 102
Figure 8-17 Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant).................. 104
Figure 8-18 Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant)................ 105
Figure 8-19 Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant).................. 106
Figure 8-20 Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant)................ 107