Intel PENTIUM P6000 - DATASHEET 2010 - Page 6

6 Datasheet
Figure 8-21 BGA1288 Ballmap (Top View, Upper-Left Quadrant) ..................................136
Figure 8-22 BGA1288 Ballmap (Top View, Upper-Right Quadrant) ................................137
Figure 8-23 BGA1288 Ballmap (Top View, Lower-Left Quadrant) ..................................138
Figure 8-24 BGA1288 Ballmap (Top View, Lower-Right Quadrant) ................................ 139
Figure 8-25 rPGA Mechanical Package (Sheet 1 of 2) ................................................. 177
Figure 8-26 rPGA Mechanical Package (Sheet 2 of 2) .................................................. 178
Figure 8-27 BGA Mechanical Package (Sheet 1 of 2) ...................................................179
Figure 8-28 BGA Mechanical Package (Sheet 2 of 2) ...................................................180
Tables
Table 2-1 Supported SO-DIMM Module Configurations1..............................................19
Table 2-2 DDR3 System Memory Timing Support ......................................................20
Table 2-3 eDP/PEG Ball Mapping .............................................................................32
Table 2-4 Processor Reference Clocks ......................................................................34
Table 4-5 System States........................................................................................36
Table 4-6 Processor Core/Package State Support ......................................................36
Table 4-7 Integrated Memory Controller States.........................................................37
Table 4-8 PCIe Link States .....................................................................................37
Table 4-9 DMI States ............................................................................................37
Table 4-10 Integrated Graphics Controller States ........................................................37
Table 4-11 G, S and C State Combinations.................................................................38
Table 4-12 D, S, and C State Combination .................................................................38
Table 4-13 Coordination of Thread Power States at the Core Level ................................41
Table 4-14 P_LVLx to MWAIT Conversion ...................................................................41
Table 4-15 Coordination of Core Power States at the Package Level...............................44
Table 4-16 Targeted Memory State Conditions............................................................48
Table 5-17 Intel Pentium U5000 mobile processor series Dual-Core ULV Thermal Power
Specifications .........................................................................................53
Table 5-18 Intel Pentium P6000 mobile processor series Dual-Core SV Thermal Power
Specifications .........................................................................................54
Table 5-19 18 W Ultra Low Voltage (ULV) Processor Idle Power ....................................54
Table 5-20 35 W Standard Voltage (SV) Processor Idle Power.......................................54
Table 6-21 Signal Description Buffer Types ................................................................68
Table 6-22 Memory Channel A..................................................................................69
Table 6-23 Memory Channel B..................................................................................70
Table 6-24 Memory Reference and Compensation .......................................................71
Table 6-25 Reset and Miscellaneous Signals ...............................................................72
Table 6-26 PCI Express Graphics Interface Signals ......................................................73
Table 6-27 Intel® Flexible Display Interface...............................................................74
Table 6-28 DMI - Processor to PCH Serial Interface .....................................................75
Table 6-29 PLL Signals ............................................................................................75
Table 6-30 TAP Signals............................................................................................76
Table 6-31 Error and Thermal Protection....................................................................77
Table 6-32 Power Sequencing ..................................................................................78
Table 6-33 Processor Power Signals ..........................................................................79
Table 6-34 Ground and NCTF ...................................................................................81
Table 6-35 Processor Internal Pull Up/Pull Down .........................................................81
Table 7-36 Voltage Identification Definition ................................................................84
Table 7-37 Market Segment Selection Truth Table for MSID[2:0] ..................................87
Table 7-38 Signal Groups1.......................................................................................88
Table 7-39 Processor Absolute Minimum and Maximum Ratings ....................................92