JVL MAC00-EC41 - Page 294

294 JVL Industri Elektronik A/S - User Manual - Ethernet for MAC and MIS motors
12.4 Motor registers MISxxx
Reg Name Size Access Range Default Unit Description MacTalk
name
35 ERR_BITS 32bit R/W 0 Special Errorbits:
Bit0:Generalerror(alwayssettogetherwithanother
errorbit)
Bit1:Followerror
Bit2:Outputdriver
Bit3:PositionLimit
Bit4:Lowbusvoltage
Bit5:Overvoltage
Bit6:Temperature>90°C
Bit7:Internal(Selfdiagnosticsfailed)
Bit8:Absolutemultiturnencoderlostposition
Bit9:Absolutemultiturn
encodersensorcounting
Bit10:Nocomm.toabsolutemultiturnencoder
Bit11:SSIencodercounting
Bit12:Closedloop
Bit13:Externalmemory
Bit14:Absolutesingleturnencoder
Bit27:SafeTorqueOff(STO)
Errors
36 WARN_BITS 32bit R/W 0 Special Warningbits:
Bit0:Positivelimitactive
Bit1:Negativelimitactive
Bit2:Positivelimithasbeenactive
Bit3:Negativelimithasbeenactive
Bit4:Lowbusvoltage
Bit5:Reserved
Bit6:Temperature>80°C
Bit7:SSIencoder
Bit8:Driveroverload
Warnings
37 STARTMODE 32bit R/W 0,1,2,30‐ Themotorwillchangetoth ismodeafterpowerup.This
isalsothemodethatisusedafterazero
searchis
completed.
SeeMODE_REGforalistofpossiblemodes.
Startupmode
38 P_HOME 32bit R/W
(‐2
31
)‐(2
31
‐1)
0StepsThefoundzeropointisoffsetwiththisvalue. Zerosearch
position
39 Reserved (intendedfor64‐bitP_HOMEhi‐word)
40 V_HOME 32bit R/W ‐300,000‐300,000 ‐5000 0.01
RPM
Thevelocitytouseduringzerosearch.Setanegative
velocitytosearchinthenegativedirection.
Zerosearch
velocity
42 HOMEMODE 32bit R/W 0,13,14 0 ‐ Selectthezerosearchthatshouldstarton
powerup. Zerosearch
mode
43‐
45
Reserved 32bit R/W 1‐8 0 Planned‐Notsupportedyet!
46 AbsEncPos 32bit R 0‐409,500 0 Steps Thepositionlastreadfromtheinternalmagnetic
encoder.Thisistheabsolutesingle‐turnposition.
Abs.encoder
position
47 EXTENCODER 32bit R
(‐2
31
)‐(2
31
‐1)
0 Counts Thevaluefromanexternalencoder,eg.SSI. SSIEncoder
value
48 FlexReg 32bit R ‐ 0 ‐ Amixof16bitsfromdifferentregisters.Theusercanset
thisup.
49‐
64
Pn 32bit R/W
(‐2
31
)‐(2
31
‐1)
0Steps8positionregisters(oddnumberedregisters) Positionn(Pn)