Keithley 2000 Repair Manual

Test 401.1 — INVERT PATH
Bank VAC
Inputs Open
Expected Value <none specified>
Limits <none specified>
Fault Message <none>
Description This test places the ACV front end in the inverting configuration. Logic
levels for this configuration are as follows:
K102: /SETK1 high, /RESETK1 low
U103: Pins 8 and 9 high
U105: Pin 9 low
The signal path is from ACIN through C105, R104 and R105, which make
up a 1.1MΩ input resistance to the minus input of op amp U102. The plus
input of U102 is connected to AC common through R146. Feedback for
U102 is provided by R106 (11kΩ). The output gain for U102 (seen at ACFE)
is ×0.001 (R106/(R117+R104+R105)).
The output of U102 (ACFE) is routed through U103 (pin 1 low) to U112
which is configured for ×10 gain. The signal then goes through U105 (pin 1
low) and is coupled across C115 to U118 which is configured for ×2 gain.
The output of U118 goes to the TRMS converter (U110) through the par-
allel combination of R129, C113 and C114. The output of the TRMS con-
verter (OUT) is fed back through its own internal buffer. The buffer output
signal (BUFF OUT) is then labeled AC_MED. The AC_MED signal is se-
lected at U163 and fed to the A/D buffer (U166) through Q117. The A/D
buffer is set up for ×1 gain through U129 (/×1 low). This test is a setup phase
for the next test.
Bit patterns
Bit pattern Register
QQ
87654321
—U106—
101v1101
QQ
87654321
—U109—
01101111
QQ
87654321
—U134—
1v01000v
—U130—
10011101
QQ
87654321
—U121—
01110000
ACDC_STB
MUX_STB
IC pins: Q8=11, Q7=12, Q6=13, Q5=14, Q4=7, Q3=6, Q2=5, Q1=4
Troubleshooting 2-43

Keithley 2000 Specifications

General

Digits	6.5
DC Voltage Range	100 mV to 1000 V
AC Voltage Range	100 mV to 750 V
Resistance Range	100 Ω to 100 MΩ
Connectivity	IEEE-488 (GPIB)
Display Type	VFD