Lexicon LXP-5 Service Manual

Circuit
Description
Lexicon
Reset Circuitry The reset circuitry insures proper operation of the LXP-5 during powerup and
power fail conditions. This circuitry monitors the +5VUNREG supply and
provides ZRST, ZRST/, MRST/ and RCE command signals.
The +5VUNREG supply is filtered by FB3 and Cl 7 to prevent noise spikes on
the AC line from tripping the reset function. R17 and R18 create a voltage
divider which feeds C11 and the base of transistor Q3. C11 provides low
frequency filtering for the base voltage. Q3 has a common emitter configura¬
tion with a pull-up resistor (R11) to +5 VDC on its collector. The collector
voltage is applied to the input of a Schmitt inverter (U1, pin 3) whose output
provides feedback to the base of Q3 through R12. During power up Q3 is off
until the +5VUNREG supply exceeds the level necessary to bring the
transistor into its active state. At this time, the collector voltage starts to drop,
which causes the inverter output to go high and turns Q3 on. During a power
fail or low power sequence, the +5VUNREG supply starts to drop, bringing Q3
out of saturation and into its active state. The collector voltage starts to
increase which causes the inverter output to go low and turns the transistor
off.
With the supplied 120 VAC power pack, an AC line voltage above 100 volts
will turn Q3 on and insure the proper power up sequence for the LXP-5
circuitry. If the AC line voltage drops below 100 volts, Q3 turns off, enabling
the required reset signals.
The collector of Q3 provides the ZRST command signal. ZRST is applied to
the UART’s Reset pin (U3, pin 21) and the Battery Backup circuitry, which
require an active high signal for reset to occur.
The inverter output (U1, pin 4) provides the ZRST/ command signal. ZRST/
is applied to the Lexichip’s Reset pin (U21 pin 74) which requires an active low
signal for reset to occur. The ZRST/ command is also used to clear a latch
(U5) and the MIDI timer (U13).
ZRST is also applied to another inverter input (U1,pin 13) through a delay
circuit made up of CR5, CIO and R5. The output of this inverter provides the
MRST/ command signal. MRST/ is used to reset the Master Z80 Processor
(U4, pin 26) which requires an active low signal. The Master Z80 Processor
is the last device enabled bythe LXP-5 Reset circuitry, due to the delay circuit
associated with MRST/. This insures that all other devices are in a known
active state when the Master Z80 (U4) is enabled.
MRST/ is also used to provide RCE, which is the SRAM Chip Enable. RCE
is controlled by Q1. The collector of Q1 is connected to the chip enable pins
of the SRAMs (U17 & U20, pin26), and provides the RCE command signal.
MRST/ is applied to the emitter of Q1 through R4. The base of the transistor
is biased by CR2 and R3. Upon power up, MRST/ will go high after a delay,
causing RCE to go high and enabling the SRAMs. The delay provided by
MRST/ allows the SRAM VCC to stabilize before they are enabled. MRST/
and RCE immediately go low upon power fail, before +5 VDC goes out of
regulation and the SRAM VCC drops to +3 volts.
The 74HCT14 hex inverter (U1) is an important component in the LXP-5
Reset circuitry. Therefore, its power supply is independent from the +5 VDC
supply. CR3,R6andC5 provide a separate 4.7VDC supply to insure proper
operation of U1 for a brief time during a power fail condition.
3-4

Lexicon LXP-5 Specifications

General

Brand	Lexicon
Model	LXP-5
Category	Recording Equipment
Language	English