Lexicon LXP-5 - Master Decoding.3-12

Circuit
Description Lexicon
Master Decoding
Master Decoding Chart
U11, a PAL16L8 decodes address bus signals of the Master 280 into
memory and I/O device signaling. Two AND gates (U18) ,an inverter (U1)
and a 74HCT174 D latch (U5) are also utilized in this function. The chart
below shows the PAL decoding scheme for Memory and I/O operations. A
description of each output signal provided by the Master Z80 decoding
circuitry is also provided at the end of this section.
MASTER PAL DECODING CHART: (MMREQ/ = L) MEMORY
MADR: 15 14
13
HEX ADDRESS
Active Sel Line H/L
0
0
0
1
0
1
through
7FFFh
ROM/
L
1
0
1
AOOOh
through
BFFFh
RAM/
L
1
1
0
COOOh
through
DFFFh
MSREQ/
SLAVE PAL DECODE:
SRAM /
L
1
1 1
EOOOh
through
E3FFh
MSREQ/
SLAVE PAL DECODE:
LEX/
L
MASTER PAL DECODING CHART: (MIORQ/ = L)
I/O
MADR:
7 6 5
HEX ADDRESS
Active Sel Line
R/W
H/L
0 0 0
OOh
101/ R L
0 0
1
20h
102/ R L
0
1
0
40h
103 R H
0
1 1
60h
MDB
7 6 5 4 3 2 1 0
104
w H
X X
X
2. X X X
Q-
MSYNC/
X
I
X
X X X X X 0 X
MUTE/ X L
X
X X
x_
X 0 X X SRST/
X L
0 1
MIDI LED=GREEN
1
0 MIDI LED=RED
0 0
MIDI LED=OFF
T" I hl'il II 1
1 0 0
80h
UART/
R/W L