Lexicon LXP-5 Service Manual

Circuit
Description
Lexicon
Slave Processor Functions The Slave Z80 (U14) is strictly dedicated to controlling Lexichip operations.
This task is performed by accessing the Lexichip Writeable Control Store, the
on-chip memory and register storage which is connected to the Slave Z80
bus via a Read/Write port.
Memory 32K bytes of ROM space is contained in a single 27C256 PROM (U10). This
ROM is mapped into the Master processor memory space. It contains Slave
Z80 and Lexichip program routines which are loaded by the Master Z80 via
the Master/slave interface. Diagnostics, I/O, and housekeeping subroutines
executed by the Master Processor are also contained in this ROM space.
Two CMOS 4364C SRAM ICs (U17, U20) provide a total of 16K of RAM
space for both Z80 processors. This RAM is kept non-volatile by the Battery
Backup circuitry explained in the power supply section of this chapter. All 16K
bytes of RAM are mapped into the M aster Z80 memory space. Because U20
is connected to the Slave bus, the Master Z80 must access this upper 8K of
RAM via the Master/Slave interface explained below. Only the upper 4K of
RAM contained in U20 is mapped into the Slave Z80’s memory space to
function as both program and data memory for that processor. Slave Z80
code is loaded into memory by the Master Z80. The lower 4K of space
contained in U20 serves as user-register storage. This is managed by the
Master processor and cannot be accessed by the Slave Z80.
The Lexichip (U21) contains its own on-chip program RAM and I/O registers
which are addressable by both Z80 processors via the Slave Bus. This 1K
byte of memory is mapped into the 64K of addressable memory space of
both Master and Slave processors.
3-10

Lexicon LXP-5 Specifications

General

Brand	Lexicon
Model	LXP-5
Category	Recording Equipment
Language	English