Lexicon LXP-5 - Master;Slave Interface

LXP-5 Service Manual
Circuit
Description
A memory refresh period is produced by a Z80 processor for two clock cycles Master/Slave interface
during every instruction fetch. Since the static RAM used by the Master and
Slave Z80s does not require refreshing, the master processor utilizes the
Slave Z80’s available refresh period to gain access to the Slave processor
bus in a manner that is completely transparent to Slave operations. Syncroni-
zation of timing for Master Z80 access to the Slave Bus is performed by the
Slave Decoding PAL (U6).
The following diagram illustrates the actual hardware interface.
Master /Slave Interface Diagram
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