Lexicon LXP-5 - Slave Decoding

LXP-5 Service Manual
Circuit
Description
The Slave PAL (U6) handles the Mapping of the Slave RAM and Lexichip Slave Decoding
WCS into both 280 processors’ memory. Address and control signals on the
Slave Bus are decoded as shown below.
Master Z80 access to the Slave Bus is also controlled by the Slave PAL.
Access is synchronized to occur during the memory refresh period of the
Slave Z80 by forcing wait states on the Master Z80. This is also illustrated in
the timing diagram in the following section.
Slave Decoding Chart
SLAVE PAL DECODING CHART