Lexicon LXP-5 - LXP-5 Lexichip and System Interfaces

Circuit
Description
Lexicon
Digital Audio
Processor Circuitry
LEXICHIP: Z80 Interface
Clocks
Audio Memory
LEXICHIP: DAC/ADC Control
Logic and Data Port
The Lexichip (U21) performs all the digital effects processing calculations for
the LXP-5. It receives instructions from its internal program RAM, referred to
as the Writeable Control Store (WCS). Address, data, and control lines for the
WCS are shared with the Slave Z80 bus. This allows both Slave and Master
Z80 processors to load audio effects programs into the Lexichip, monitor
status of audio data, and synchronously change program parameter values
in audio programs. Both Master and Slave Z80 processors treat the 1K bytes
of WCS as mapped memory space.
An internal crystal oscillator driver circuit drives a 16MHz crystal mounted
across pins 75 and 76 on the Lexichip. Internal Lexichip circuitry divides this
clock frequency down to provide the 4MHz ZCLK which is used by the Z80
processors.
The PCLK1 (pin 73) output is programmed to divide down the 16MHz clock
to the 500kHz MIDICLK signal. This signal is utilized by the UART 1C (U3) to
set up the serial communications baud rate.
WC/ (pin 59) is used as a clock reference by the LXP-5. It operates at a 31.25
kHz sample rate and is utilized by the UART interrupt timing circuitry, as well
as by the Slave decoding circuitry, to sync the Master processor to DSP
operations.
Four64Kx 4-bit dynamic RAM ICs(U22,U23,U29,U30) provide the 64Kx 16-
bit RAM space used by the Lexichip for audio data storage. DRAM read, write,
and refresh functions are performed by a dedicated set of address and control
lines and a 16-bit data bus provided by the Lexichip.
Internal control logic circuitry enables the Lexichip to command complete
control over external DAC functionality with minimal external circuitry.
Two 8 bit latches (U27.U28) are used to latch 16 bit data out to the DAC via
the DRAM data bus. Lexichip output CCLK1 clocks DAC data into these DAC
conversion latches.
An internal Successive Approximation Register (SAR) allows the DAC, in
conjunction with an externa! comparator, to perform analog to digital conver¬
sions. A data value is latched into the conversion latch. DAC output is
compared to analog input by the comparator. The comparator's resulting
output (DATA) is applied to Lexichip input SI1, and the SAR logic circuitry
determines either the next DAC output value or an end of conversion.
Converted data is then processed by the Lexichip with instructions from its
RAM resident digital effects program.
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