Lexicon LXP-5 - Page 44

LXP-5 Service Manual
Circuit
Description
Interrupt
Request/Acknowledge
Cycle
A Master 280 requests an Interrupt
from the Slave processor
B Master Z80 requests Slave Bus
Access. Since this request is not syn-
cronous with a Refresh window,
MWAiT/ is activated. Master 280
inserts wait states until the next
available window.
C SMI goes low as the beginning of an
interrupt acknowledge cycle is oc¬
curring. in the interrupt mode used
by the Slave 280, its data bus will be
in a high impedance state during this
entire cycle.
D SMI/ is low for 4 T states during the
Interrupt Acknowledge cycle. Due to
this extended SMI, the Master280 can
request Slave Bus Access (by activat¬
ing MSREQ/) and gain access without
wait states during the last 3 T-states of
SMI/.
E SIORQ/ goes low. This, in conjunction
with SMI/ staying low for an additional
two wait periods, creates the Interrupt
Acknowledge signal.
F SMI/ and SIORQ/ both go high, indi¬
cating Refresh period has begun.
G If MSREQ/ls low during ST4, MWAiT
will become active. This wait will be
ignored by the Master 280 if
MSREQ/ went low on the last SW
clock before Refresh, as the Master
has already gained access. If
MSREQ/ goes low during ST3, wait
states will be inserted by the Master
280 until the next Refresh window
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