Lexicon LXP-5 - Page 49

Circuit
Description
Lexicon
SRAM/ U6 Pin 19 [L]
Slave RAM enable. Activates Slave RAM 1C ,1120.
MWAIT/ U6 Pin 14 [L]
Master Z80 WAIT. This signal is activated by one of the following two
conditions:
If MSREQ/ is asserted outside the Slave Z80 refresh period MWAIT will force
the Master Z80 to insert wait states until the next available Slave refresh
period before gaining access to the Slave Bus.
When MSYNC is asserted by the Master Processor, MWAIT will force the
Master Z80 to insert wait states until the falling edge of WC/.
MACC/ U6 Pin 16 [L]
Master access. In a low state , this signal disables Slave Z80 address bus
buffers (U8, U15) and enables Master Z80 address buffers (U9, U16) and
data bus buffer (U7), thereby allowing Master Processor access to Slave bus.
This active low state occurs if MSREQ/ has been asserted AND either a Slave
Refresh period occurs or Slave reset (SRST/) is activated.
UCLK U6 Pin 17
UART Clock. The 4MHz ZCLK input is divided by two to create this 2MHz
UART clock.
Signal Glossary
CAS/ Column address strobe low (from Lexichip)
CAS1/ Column address strobe 1 low (to DRAMs)
DAB <0:1 5 > Digitized audio bus (from Lexichip)
DAC <0:1 5 > Digitized audio bus (to D/A Converter)
DATA Serial audio data (from comparator)
DEGO Deglitch 0
DEG1 Deglitch 1
FOOT/ Footswitch low
INTACK/ Interrupt acknowledge low
101/ Input/Output enable 1 low
102/ Input/Output enable 2 low
103 Input/Output enable 3
104 Input/Output enable 4
LEX/ Lexichip enable low
LRADR <0:12> Lexichip RAM address bus
LRCB Lexichip RAM control bus
LRMREQ/ Lexichip RAM memory request low
LRRD/ Lexichip RAM read low
LRWR / Lexichip RAM write low
MA <0:7> Audio memory address bus
MACC/ Master Z80 access low
MADR <0:15> Master Z80 address bus
MCB Master Z80 control bus
MDB <0:7> Master Z80 data bus
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