Microchip Technology Microsemi miSLIC Le9642 - ZLR964222 L Rev B0 Layout Plots; Figure 28 - Top Etch and Silk Screen; Figure 29 - Bottom Etch and Silk Screen

ZLR964222L Line Module User Guide
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Microsemi Corporation Confidential and Proprietary
7.5 ZLR964222L Rev B0 Layout Plots
Plots of the layout of the ZLR964222L Line Module are provided in this section. This layout is available in Cadence
Allegro .brd (V16.5) format upon request. The gerber files are also available.
Figure 28 - Top Etch and Silk Screen
Figure 29 - Bottom Etch and Silk Screen