EasyManua.ls Logo

Mitsubishi Electric MELSEC iQ-RJ71C24-R2 - How to Clear Programmable Controller CPU Information

Mitsubishi Electric MELSEC iQ-RJ71C24-R2
574 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
27 TROUBLESHOOTING
27.2 How to Clear Programmable Controller CPU Information
455
27
27.2 How to Clear Programmable Controller CPU
Information
This section explains how to clear the programmable controller CPU information.
Programmable controller CPU information
This is the information about the access target CPU module type used for communications using MC protocol.
C24 obtains this information from the access target CPU module at the time of initial access, and stores it inside the C24.
When accessing for the second time or later, the processing to access to the CPU module get faster in accordance with this
information.
The programmable controller CPU information is cleared in the following cases:
When the programmable controller is powered OFF ON, or when the CPU module is reset
When the programmable controller CPU information clear request is executed
If the programmable controller CPU information has not been correctly obtained
The following problems may occur:
Accessible device range become narrowed. (Error code: 7140H)
Some of commands and/or devices cannot be used. (Error code: 7142H, 714DH),
etc.
In the above case, execute the programmable controller CPU information clear request.
If initial access is made at startup of the access target CPU module or while the network is unstable, the
programmable controller CPU information may not be correctly acquired.
Operation of the programmable controller CPU information clear request
Write "4C43H" to the 'Programmable controller CPU information clear request' (Un\G128). (Set by the user)
The programmable controller CPU information clear processing of C24 is performed.
*1
Upon completion of the clear processing, "0000H" is written to the 'Programmable controller CPU information clear request'
(Un\G128). (Set by the C24)
*1 The 'Transmission sequence status' (Un\G597/613) is also initialized.
b15 b0
Un\G128
Buffer memory address
(Default: 0000H)
Write 4C43H
0000H: No request (Set by C24)
4C43H: Requested
to
0000
H
0000
H
4C43
H
Clear request
Un\G128
Buffer memory address
Clear processing

Table of Contents

Other manuals for Mitsubishi Electric MELSEC iQ-RJ71C24-R2

Related product manuals