6. BASIC INSTRUCTIONS
6 − 66
MELSEC-A
EI
(1) Enables the interrupt program.
IRET
(1) Indicates the termination of processing of interrupt program.
(2) Performs the processing of counter for interruption and returns the processing
to the sequence program after the RET instruction is executed.
With the CPUs other than A3H, A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and
A2USH board interrupt counter processing is performed.
POINTS
(1) When a counter is used in the interrupt program, use the counter for
interruption.
The A3H, A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board do
not have any counter which may be used in the interrupt program.
(2) The pointer for interruption occupies one step.
(3) For the interrupt conditions, refer to the ACPU Programming Manual
(Fundamentals).
(4) During the execution of interrupt program, DI (interruption inhibition) is set.
Do not allow multiple interrupt programs to be run simultaneously. This can
be prevented by using the EI instruction in the interrupt programs.
(5) If the EI or DI instruction is contained in the MC instruction, such EI and DI
are executed without regard to execution of the MC instruction.
(6) For the PC CPUs shown below, setting indicated below is required.
• A0J2HCPU, AnSCPU, AnSHCPU, A2CCPU, AnCPU, AnNCPU, A3HCPU,
A3MCPU, A3VCPU
In a sequence between the IRET instruction in a interrupt program and the
END instruction at the end of a sequence program, a dummy circuit must
always be set. Otherwise, the PC will fail to operate correctly.
(A NOP instruction has the same effect. However, take it into consideration
that "NOP batch deletion" must not be executed by a peripheral device.)
Sequence program
Sequence program
Interrupt program
DI
EI
FEND
In
Any interrupt signal occuring between
DI and EI instructions, is disabled
until the processing between the DI
and EI instructions is completed after
which the interrupt program is run.
()
(
)
I10
50
X00C
X005
Y010
Y030
IRET
53
55
Stored into
step 50.
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