Mitsubishi MELSEC-A series - Page 29

2. INSTRUCTIONS
2 − 13
MELSEC-A
(3) BCD ↔ BIN conversion instructions
Table 2.12 BCD ↔ BIN Conversion Instructions
Classi-
fication
Unit
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Number of steps
Index
Subset
Applicable CPU Page
BCD 5
● ●
!
6-39
16 bits
BCDP
BCD conversion
(S) (D)
BIN (0 to 9999)
5
● ●
!
6-39
DBCD 9
●
!
6-39
BCD
conver-
sion
32 bits
DBCDP
BCD conversion
(S1+1, S1) (D+1, D)
BIN (0 to 99999999)
9
●
!
6-39
BIN 5
● ●
!
6-42
4-digits
BINP
BIN conversion
(S) (D)
BCD(0 to 9999)
5
● ●
!
6-42
DBIN 9
●
!
6-42
BIN
conver-
sion
8-digits
DBINP
BIN conversion
(S1+1, S1) (D+1, D)
BCD (0 to 99999999)
9
●
!
6-42
(4) Data transfer instructions
Table 2.13 Data Transfer Instructions (Continue)
Classi-
fication Unit
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Number of steps
Index
Subset
Applicable CPU Page
MOV 5
● ●
!
6-47
16 bits
MOVP
(S) → (D)
5
● ●
!
6-47
DMOV 7
● ●
!
6-47
Transfer
32 bits
DMOVP
(S+1, S) → (D+1, D)
7
● ●
!
6-47
CML 5
● ●
!
6-49
16 bits
CMLP
(S) → (D)
5
● ●
!
6-49
DCML 7
● ●
!
6-49
Nega-
tion
transfer
32 bits
DCMLP
(S+1, S) → (D+1, D)
7
● ●
!
6-49
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The
mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The
mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*1
*3
*3
*1