2. INSTRUCTIONS
2 − 15
MELSEC-A
(6) Program switching instruction
Table 2.15 Program Switching Instruction
Classi-
fication
Unit
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Number
of steps
Index
Subset
Applicable CPU Page
Switch-
ing
CHG
Switches between the main and
subprograms.
1
Not applicable to AnS, AnSH, A1FX,
A1, A2(S1), A1N, A2N(S1),
A2N(S1), A2A(S1), A2A(S1), A2C,
A0J2H and A52G.
6-70
(7) Refresh instructions
Table 2.16 Refresh Instructions
Classi-
fication
Unit
Instruction
Symbol
Symbol Contents of Processing
Execu-
tion Con-
dition
Number
of steps
Index
Subset
Applicable CPU Page
Link
refresh
COM
Executes refresh, general data
processing.
3 Not applicable to A3V. 6-83
EI
Enables link refresh. Valid when
M9053 is on.
1
Not applicable to An, A3H, A3M,
A3V, AnA, A2AS, AnU, QCPU-A
(A Mode) and A2USH board.
6-85
Link
refresh
enable,
disable
DI
Disables link refresh. Valid when
M9053 is on.
1
Not applicable to An, A3H, A3M,
A3V, AnA, A2AS, AnU, QCPU-A
(A Mode) and A2USH board.
6-85
Partial
refresh
SEG
Only executes refresh for the
corresponding device during 1 scan.
Valid when M9052 is on.
7
Not applicable to An and A3N
board.
6-88
*1: For the number of steps when extension devices are used or when index qualification is performed to
bit devices for AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board, refer to Section 3.8.1.
*2: The
mark in the Index column indicates that index qualification can be performed with the AnA,
A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*3: The
mark in the Subset column indicates that subset processing can be performed with the A3H,
A3M, AnA, A2AS, AnU, QCPU-A (A Mode) and A2USH board only.
*1
A3H,
A3M, A3A
CPUs other
than above
*1
*2
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