Mitsubishi MELSEC-A series - Page 484

APPENDICES
APP − 79
MELSEC-A
Table 2.6 Instruction Processing Time of CPUs (Continue)
Processing Time (µs)
An
AnN, A3V, A73
A3N Board
A3H, A3M A2A, A2U
A3A
A3U, A4U
D D
Instruction Condition
D R
Other
than
X, Y
X, Y
R
Other
than
X, Y
X, Y
R R
SLT
Only
device
memory
 8448 8448 8448 4100* 4100* 4100* 2915 2186
SLT
Device
memory
+R
 24598 24598 24598 10400* 10400* 10400* 9996 7497
SLTR  29 29 29 53* 53* 53* 6.6 5.0
STRA  30 30 30 52* 52* 52* 5.0 3.8
STRAR  28 28 28 52* 52* 52* 5.0 3.8
STC  28 28 28 1.2 1.2 1.2 2.4 1.8
CLC  31 31 31 1.2 1.2 1.2 2.4 1.8
DUTY  68 68 68 121* 121* 121 14 11
PR  226 226 226 183* 183* 183* 74 59
PRC  141 141 141 145 145 145 37 31
CHK
Bit reverse
output instruction
 121 121 121     
LED 170 203 203 203 282* 282* 282* 100 75
LEDC 210 265 265 265 320* 320* 320* 142 109
LEDA 170 202 202 202 262* 262* 262*  
LEDB 172 211 211 211 262* 262* 262*  
LEDR 520 638 638 638 460* 460* 460* 106 80
R: Refresh mode, D: Direct mode
* With an A3M, processing time will be 20µs longer than the indicated time.