Mitsubishi MELSEC Q Series - Page 838

Index - 4
H
High Performance model QCPU . . . . . . . . . . . . . .1-5
High-speed Block Transfer of File Register . . . . .7-451
How to Read Instruction Tables . . . . . . . . . . . . . . .2-4
HOW TO READ INSTRUCTIONS . . . . . . . . . . . . .4-1
I
I/O refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . .6-145
I/O Refresh Instructions . . . . . . . . . . . . . . . . . .6-145
Identical 16-bit data block transfers . . . . . . . . . .6-122
Identical 32-bit data block transfers . . . . . . . . . .6-125
Incrementing and decrementing 16-bit BIN data . .6-70
Incrementing and decrementing 32-bit BIN data . .6-72
Index modification of entire ladder . . . . . . . . . . .7-143
Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12
Indexing with 16-bit index registers . . . . . . . . . . .3-12
Indexing with 32-bit . . . . . . . . . . . . . . . . . . . . . .3-13
Indirect address read operations . . . . . . . . . . . .7-394
Indirect Specification . . . . . . . . . . . . . . . . . . . . .3-23
Insertion of character string . . . . . . . . . . . . . . . .7-240
Instructions whose designation format has been
changed . . . . . . . . . . . . . . . . . . . . . . . . . . App-146
Intelligent function module. . . . . . . . . . . . . . . . . . .1-7
Intelligent function module device . . . . . . . . . . . . .1-7
Interrupt disable/enable instructions, interrupt
program mask . . . . . . . . . . . . . . . . . . . . . . . . .6-136
J
Jump to END. . . . . . . . . . . . . . . . . . . . . . . . . .6-135
L
L series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
Ladder block series connection and parallel
connection
. . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10
LCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
Leading edge and trailing edge outputs . . . . . . . .5-37
Left rotation of 16-bit data . . . . . . . . . . . . . . . . . .7-38
Left rotation of 32-bit data . . . . . . . . . . . . . . . . . .7-44
Linking character strings . . . . . . . . . . . . . . . . . . .6-66
List of arithmetic operation instructions . . . . . . . . .2-16
List of association instructions . . . . . . . . . . . . . . . .2-7
List of bit processing instructions . . . . . . . . . . . . .2-34
List of buffer memory access instructions . . . . . . .2-41
List of character string processing instructions. . . .2-43
List of clock instructions . . . . . . . . . . . . . . . . . . .2-52
List of comparison operation instructions . . . . . . .2-10
List of contact instructions . . . . . . . . . . . . . . . . . . .2-6
List of data control instructions . . . . . . . . . . . . . .2-49
List of data conversion instructions. . . . . . . . . . . .2-22
List of data processing instructions. . . . . . . . . . . .2-35
List of data transfer instructions . . . . . . . . . . . . . .2-24
List of debugging and failure diagnosis instructions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-42
List of display instructions . . . . . . . . . . . . . . . . . .2-41
List of expansion clock instructions . . . . . . . . . . .2-55
List of I/O refresh instructions . . . . . . . . . . . . . . .2-27
List of instructions for Multiple CPU high-speed
transmission dedicated
. . . . . . . . . . . . . . . . . . . .2-61
List of instructions for Network refresh . . . . . . . . .2-59
List of instructions for reading from the CPU
shared memory of another CPU . . . . . . . . . . . . . 2-60
List of instructions for reading/writing routing
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
List of instructions for Redundant system
(For Redundant CPU)
. . . . . . . . . . . . . . . . . . . . 2-62
List of instructions for writing to the CPU shared
memory of host CPU
. . . . . . . . . . . . . . . . . . . . . 2-60
List of logical operation instructions . . . . . . . . . . . 2-29
List of master control instructions . . . . . . . . . . . . . 2-9
List of other convenient instructions . . . . . . . . . . . 2-28
List of other instructions . . . . . . . . . . . . . . . .2-9,2-57
List of output instructions . . . . . . . . . . . . . . . . . . . 2-8
List of program branch instructions . . . . . . . . . . . 2-27
List of program control instructions . . . . . . . . . . . 2-56
List of program execution control instructions . . . . 2-27
List of rotation instructions . . . . . . . . . . . . . . . . . 2-32
List of shift instructions . . . . . . . . . . . . . . . . . 2-8,2-33
List of special function instructions. . . . . . . . . . . . 2-46
List of structure creation instructions . . . . . . . . . . 2-38
List of switching instructions . . . . . . . . . . . . . . . . 2-51
List of table operation instructions . . . . . . . . . . . . 2-40
List of termination instructions . . . . . . . . . . . . . . . . 2-9
Load + Unload. . . . . . . . . . . . . . . . . . . . . . . . . 7-448
Load Program from Memory Card . . . . . . . . . . . 7-443
Logical products with 16-bit and 32-bit data . . . . . . 7-3
Logical sums of 16-bit and 32-bit data . . . . . . . . . 7-11
M
Master Control Instructions . . . . . . . . . . . . . . . . . 5-47
Matrix input . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-170
Maximum value search for 16- and 32-bit data . . . 7-89
MELSECNET(II/,B) . . . . . . . . . . . . . . . . . . . . . . . 1-6
MELSECNET/10 . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
MELSECNET/H. . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Minimum value search for 16- and 32-bit data. . . . 7-92
Multiplication and division of floating decimal point
data (Double precision) . . . . . . . . . . . . . . . . . . . 6-56
Multiplication and division of floating decimal point
data (Single precision)
. . . . . . . . . . . . . . . . . . . . 6-54
N
Natural logarithm operation on floating-point data
(Double precision)
. . . . . . . . . . . . . . . . . . . . . . 7-297
Natural logarithm operation on floating-point data
(Single precision). . . . . . . . . . . . . . . . . . . . . . . 7-295
n-bit shift to right or left of 16-bit data . . . . . . . . . . 7-46
n-bit shift to right or left of n-bit data . . . . . . . . . . . 7-51
n-bit shift to right or left of n-word data . . . . . . . . . 7-56
No operations . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
Number of devices and number of transfers (n). . . . 3-2
Numerical key input from keyboard . . . . . . . . . . 7-395
O
Operation Processing Time
Basic Model QCPU
. . . . . . . . . . . . . . . . . . . .App-3
High Performance Model QCPU/Process
CPU/Redundant CPU
. . . . . . . . . . . . . . . . .App-21
LCPU . . . . . . . . . . . . . . . . . . . . . . . . . . .App-114
Universal Model QCPU . . . . . . . . . . . . . . . .App-50
Operation result conversions. . . . . . . . . . . . . . . . 5-17