NAD C 720BEE - Page 13

CD4094
MAIN BOARD:IC32&IC33
2
CL
CL
D
Q
1
CL
CL
D
Q
2
TR
TR
TR
TR
3
1
* VDD
VSS
* ALLINPUTS
PROTECTED BY
CMOS PROTECTION
NETWORK
CL
CL
8
CL
CL
n
p
DQ
Q
10
CL
CL
n
p
Q'S
SERIAL
OUT
11
Q8
TR
TR
LATCH
8
3
STATE
8
10
QS
SERIAL
OUT
STAGES
3 - 7
4
5
6
7121314
LATCH
2
3 -
STATE
2
CLOCK
*
STROBE
*
CL
CL
TR
TR
OUTPUT ENABLE
*
15
TR
TR
LATCH
1
p
n
n
VDD
VSS
Q1
Q2
Q3 Q4 Q5 Q6 Q7
3 - STSTE
1
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
STROBE
DATA
CLK
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
QS
Q'S
VSS
VDD
OUTPUT ENABLE
PIN CONFIGURATION
TL082CP/D
MAIN BOARD: IC3, IC4, IC34, IC43
-
++
-
A
B
1
2
3
45
6
7
8
V+
OUTPUT B
INVERTING INPUT B
NON-INVERTING INPUT B
V-
NON-INVERTING INPUT A
INVERTING INPUT A
OUTPUT A
KEY BOARD: IC707