•
Programmable reference clock.
•
RDS/RBDS encoder
•
Loop and monopole antenna support with self-calibrated capacitor tuning.
•
Programmable transmit level.
•
Audio dynamic range control.
System block diagram
Figure 51 FMTx 2.1 system block diagram
The figure above shows the basic system block diagram for the FMTx 2.1 implementation. _SEN is shown here
unconnected since this pin decides which I2C address is used depending on if this pin is pulled low or high.
On RM-484 the _SEN is pulled high by connecting it to VIO.
RM-484 uses a loop antenna which is located in the removable C-cover of the device. The loop antenna also
acts as the tuning inductor which is required by the Si4713 chip. The location of the antenna in the removable
cover means that ESD protection is required to prevent damage to the Si4713 device.
RM-484; RM-485; RM-486
FMTx 2.1 Technical Description
Page 6 –6 COMPANY CONFIDENTIAL Issue 1
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