Nvidia JETSON NANO - European Union Compliance; Australia and New Zealand Compliance; Japan Compliance

Platform Adaptation and Bring-Up
Jetson Nano Platform Adaptation and Bring-Up Guide DA_09361-002 | 11
A string containing the name of the function to mux to the pin or group. It must be
one of these values:
● xusb
● pcie-x1
● pcie-x4
Take Table 2, for example. Create a PCIe subnode and property under xusb_padctl
based on the device tree structure described above:
xusb_padctl@7009f000 {
...
pcie {
status = "okay"
lanes {
pcie-0 {
status = "okay"
nvidia,function = "pcie-x1";
};
pcie-1 {
status = "okay"
nvidia,function = "pcie-x4";
};
pcie-2 {
status = "okay"
nvidia,function = "pcie-x4";
};
pcie-3 {
status = "okay"
nvidia,function = "pcie-x4";
};
pcie-4 {
status = "okay"
nvidia,function = "pcie-x4";
};
pcie-5 {
status = "okay"
nvidia,function = "xusb";
};
pcie-6 {
status = "okay"
nvidia,function = "xusb";
};
};
...
};
Note:
UPHY lane 0 and UPHY lane 5 are not exposed, and can only be assigned to the
pcie-x1 and xusb functions.