Platform Adaptation and Bring-Up
Jetson Nano Platform Adaptation and Bring-Up Guide DA_09361-002 | 25
If a target UPHY Lane is not owned by the correct function, check the values of the PCIe
subnode and properties under xusb_padctl to be sure that the target lane is assigned
correctly.
Note:
Before you design your custom board, verify the lane mapping by consulting
Jetson Nano Product Design Guide.
Fan speed control mapping table
The temperature to fan speed mapping table can be modified with device tree
properties.
The fan’s thermal zone temperature is approximated by the average of the CPU and
GPU SOC thermal sensor readings. Fan speed is controlled by the PWM signal; its pulse
width range is 0-255 units.
The mapping between temperature and fan speed is defined by thermal trips and fan
cooling states. The thermal trips refer to the fan thermal zone’s temperature in degrees
Celsius, and the fan cooling state are the PWM signal’s corresponding pulse widths. You
can define trip temperatures and the corresponding cooling states by creating a custom
fan mapping table.
The fan trip temperatures are defined by the active_trip_temps property in the file:
hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-
porg-thermal-fan-est.dtsi
This example defines a set of fan thermal zone trip points:
thermal-fan-est {
name = "thermal-fan-est";
compatible = "thermal-fan-est";
status = "okay";
num_resources = <0>;
shared_data = <&thermal_fan_est_shared_data>;
trip_length = <10>;
active_trip_temps = <0 51000 61000 71000 82000
140000 150000 160000 170000 180000>;
active_hysteresis = <0 15000 9000 9000 10000
0 0 0 0 0>;
};
The fan cooling states are defined by the active_pwm property in the file:
hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-
porg-pwm-fan.dtsi
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