Platform Adaptation and Bring-Up
Jetson Nano Platform Adaptation and Bring-Up Guide DA_09361-002 | 29
Verify that any UARTs intended for debugging are enabled and functional.
Power
Verify that all supplies required on at power-on are enabled appropriately.
Verify that all supplies required off at power-on are not enabled initially.
Verify that you can enable and disable each controllable supply, and you can set
different voltage levels if applicable.
Verify that carrier board power-on sequence starts after POWER_EN signal is asserted.
Power Optimization
Capture CPU PWR Request entering and exiting Deep Sleep (LP0). Ensure that CPU
PWR Request and associated power rail sequence meets Tegra Data Sheet
requirements.
Verify that all rails that must be off in Deep Sleep (LP0) are off.
Verify that all rails that must be on in Deep Sleep (LP0) are on.
Verify that required rails are back and at correct voltage upon hardware control
exiting Deep Sleep (LP0).
USB 2.0 PHY
Verify that USB0 supports USB recovery (device mode).
Verify that USB0 device mode works with intended peripheral types, if supported.
Verify USB0, USB1 and or USB2 host mode, if implemented.
Verify USB0 Device/Host detection, if supported.
Verify that USB PHYs go to lowest power mode when not used or when the system is
in low power mode.
Verify that AVDD_USB and AVDD_PLL_UTMIP are off during Deep Sleep (LP0).
Capture USB0_D+/D- signals at both ends of link (connector and test points near
Jetson Nano).
Capture USB2_D+/D- signals at both ends of link (connector and test points near
Jetson Nano).
Using USB-IF procedures, verify that signals meet requirements (correct EYE
height/width, etc).
If USB signals do not meet requirements, use the Tegra USB Tuning Guide to adjust
settings until requirements are met.
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