NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 94
19.0 APPENDIX D: DESIGN GUIDELINE GLOSSARY
The Design Guidelines include various terms. The descriptions in the table below are intended to show w hat these terms mean
and how they should be applied to a design.
Table 92 Layout Guideline Tutorial
Max Breakout Delay
- Routing on Component layer: Maximum Trace Delay from module connector pin to point beyond pin array where normal trace spacing/impedance can be met.
Routing passes to layer other than Component layer: Beyond this, normal trace spacing/impedance must be met.
Max Total Trace Delay
- Trace from module connector pin to Device pin. This must include routing on the main PCB & any other Flex or secondary PCB. Delay is from Module connector to the
final connector/device.
Intra Pair Skew (within pair)
- Difference in delay between two traces in differential pair: Shorter routes may require indirect path to equalize delays
Inter Pair Skew (pair to pair)
- Difference between two (or possibly more) differential pairs
Microstrip vs Stripline
- Microstrip: Traces next to single ref. plane. Stripline: Traces between two ref planes
Trace Impedance
- Impedance of trace determined by width & height of trace, distance from ref. plane & dielectric constant of PCB material. For differential traces, space between pair
of traces is also a factor
Board trace spacing / Spacing to other nets
- Minimum distance between two traces. Usually specified in terms of dielectric height which is distance from trace to reference layers.
Pair to pair spacing
- Spacing between differential traces
Breakout spacing
- Possible exception to board trace spacing where different spacing rules are allowed under module connector pin in order to escape from the pin array. Outside device
boundary, normal spacing rules apply
Ground Reference Return Via & Via proximity (signal to reference)
- Signals changing layers & reference GND planes need similar return current path
- Accomplished by adding via, tying both GND layers together
Via proximity (sig to ref) is distance between signal & reference return vias
- GND reference via for Differential Pair
- Where a differential pair changes GND reference layers, return via should be placed close to & between signal vias (example to right)
Signal to return via ratio
- Number of Ground Return vias per Signal vias. For critical IFs, ratio is usually 1:1. For less critical IFs, several trace vias can share fewer return vias (i.e. 3:2 3 trace
vias & 2 return vias).
Slots in Ground Reference Layer
- When traces cross slots in adjacent power or ground plane
- Return current has longer path around slot
- Longer slots result in larger loop areas
- Avoid slots in GND planes or do not route across them
Routing over Split Power Layer Reference Layers
- When traces cross different power areas on power plane
- Return current must find longer path - usually a distant bypass cap
- If possible, route traces w/solid plane (GND or PWR) or keep routes across single area
- If traces must cross two or more power areas, use stitching capacitors
- Placing one cap across two PWR areas near where traces cross area boundaries provides high-frequency path for return current
- Cap value typically 0.1uF & should ideally be within 0.1" of crossing
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