Nvidia JETSON TX2 User Manual

NVIDIA Jetson TX2/TX2i OEM Product Design Guide
JETSON TX2/TX2i OEM PRODUCT | DESIGN GUIDE | 20180618 51
8.0 MIPI CSI (VIDEO INPUT)
Jetson TX2/TX2i supports three MIPI CSI x4 bricks, allow ing a variety of device types and combinations to be supported. Up to
three quad lane cameras or six dual lane cameras are possible (see CSI Configurations table for details). Each data lane has a
peak bandw idth of up to 2.5Gbps.
Note:
Maximum data rate may be limited by use case / memory bandwidth.
Table 46. CSI Pin Descriptions
Pin #
Module Pin Name
Tegra Signal
Usage/Description
Usage on the Carrier
Board
Direction
Pin Type
G27
CSI0_CLK
CSI_A_CLK_N
Camera, CSI 0 Clock
Camera Connector
Input
MIPI D-PHY
G28
CSI0_CLK+
CSI_A_CLK_P
Camera, CSI 0 Clock+
Input
F28
CSI0_D0
CSI_A_D0_N
Camera, CSI 0 Data 0
Input
F29
CSI0_D0+
CSI_A_D0_P
Camera, CSI 0 Data 0+
Input
H26
CSI0_D1
CSI_A_D1_N
Camera, CSI 0 Data 1
Input
H27
CSI0_D1+
CSI_A_D1_P
Camera, CSI 0 Data 1+
Input
D27
CSI1_CLK
CSI_B_CLK_N
Camera, CSI 1 Clock
Input
D28
CSI1_CLK+
CSI_B_CLK_P
Camera, CSI 1 Clock+
Input
C28
CSI1_D0
CSI_B_D0_N
Camera, CSI 1 Data 0
Input
C29
CSI1_D0+
CSI_B_D0_P
Camera, CSI 1 Data 0+
Input
E26
CSI1_D1
CSI_B_D1_N
Camera, CSI 1 Data 1
Input
E27
CSI1_D1+
CSI_B_D1_P
Camera, CSI 1 Data 1+
Input
G24
CSI2_CLK
CSI_C_CLK_N
Camera, CSI 2 Clock
Input
G25
CSI2_CLK+
CSI_C_CLK_P
Camera, CSI 2 Clock+
Input
F25
CSI2_D0
CSI_C_D0_N
Camera, CSI 2 Data 0
Input
F26
CSI2_D0+
CSI_C_D0_P
Camera, CSI 2 Data 0+
Input
H23
CSI2_D1
CSI_C_D1_N
Camera, CSI 2 Data 1
Input
H24
CSI2_D1+
CSI_C_D1_P
Camera, CSI 2 Data 1+
Input
D24
CSI3_CLK
CSI_D_CLK_N
Camera, CSI 3 Clock
Input
D25
CSI3_CLK+
CSI_D_CLK_P
Camera, CSI 3 Clock+
Input
C25
CSI3_D0
CSI_D_D0_N
Camera, CSI 3 Data 0
Input
C26
CSI3_D0+
CSI_D_D0_P
Camera, CSI 3 Data 0+
Input
E23
CSI3_D1
CSI_D_D1_N
Camera, CSI 3 Data 1
Input
E24
CSI3_D1+
CSI_D_D1_P
Camera, CSI 3 Data 1+
Input
G21
CSI4_CLK
CSI_E_CLK_N
Camera, CSI 4 Clock
Input
G22
CSI4_CLK+
CSI_E_CLK_P
Camera CSI 4 Clock+
Input
F22
CSI4_D0
CSI_E_D0_N
Camera, CSI 4 Data 0
Input
F23
CSI4_D0+
CSI_E_D0_P
Camera, CSI 4 Data 0+
Input
H20
CSI4_D1
CSI_E_D1_N
Camera, CSI 4 Data 1
Input
H21
CSI4_D1+
CSI_E_D1_P
Camera, CSI 4 Data 1+
Input
D21
CSI5_CLK
CSI_F_CLK_N
Camera, CSI 5 Clock
Input
D22
CSI5_CLK+
CSI_F_CLK_P
Camera, CSI 5 Clock+
Input
C22
CSI5_D0
CSI_F_D0_N
Camera, CSI 5 Data 0
Input
C23
CSI5_D0+
CSI_F_D0_P
Camera, CSI 5 Data 0+
Input
E20
CSI5_D1
CSI_F_D1_N
Camera, CSI 5 Data 1
Input
E21
CSI5_D1+
CSI_F_D1_P
Camera, CSI 5 Data 1+
Input
Table 47. Camera Miscellaneous Pin Descriptions
Pin #
Module Pin Name
Tegra Signal
Usage/Description
Usage on the Carrier
Board
Direction
Pin Type
F9
CAM0_MCLK
EXTPERIPH1_CLK
Camera 0 Reference Clock
Camera Connector
Output
CMOS  1.8V
F8
CAM1_MCLK
EXTPERIPH2_CLK
Camera 1 Reference Clock
Output
CMOS  1.8V
E7
CAM2_MCLK
GPIO_CAM2
Camera 2 Master Clock
Output
CMOS  1.8V
G8
GPIO0_CAM0_PWR#
QSPI_SCK
Camera 0 Powerdown or GPIO
Output
CMOS  1.8V
F7
GPIO1_CAM1_PWR#
GPIO_CAM3
Camera 1 Powerdown or GPIO
Output
CMOS  1.8V
H8
GPIO2_CAM0_RST#
QSPI_CS_N
Camera 0 Reset or GPIO
Output
CMOS  1.8V
H7
GPIO3_CAM1_RST#
QSPI_IO0
Camera 1 Reset or GPIO
Output
CMOS  1.8V
G7
GPIO4_CAM_STROBE
GPIO_SEN5
Camera Strobe or GPIO
Output
CMOS  1.8V
D7
GPIO5_CAM_FLASH_EN
UART5_RTS_N
Camera Flash Enable or GPIO
Output
CMOS  1.8V
E8
CAM_VSYNC
QSPI_IO1
Camera Vertical Sync
Output
CMOS  1.8V

Nvidia JETSON TX2 Specifications

General

Brand	Nvidia
Model	JETSON TX2
Category	Microcontrollers
Language	English