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NXP Semiconductors MCX-N9 EVK Series - DC-DC Inductor

NXP Semiconductors MCX-N9 EVK Series
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NXP Semiconductors
UM12036
MCX-N9XX-EVK Board User Manual
Description JP38 JP27 JP35 JP18 JP36 JP31 JP37 JP47 JP15
[1]
JP45
Dual IO, 3.3 V
and 1.8 V
1-2 1-2 1-2 2-3 1-2 1-2 1-2 1-2 2-3 1-2
Table 10. MCX-N9XX-EVK default power supply configuration
[1] Changing JP15 to 3.3 V requires cutting a cut trace at the bottom of the board and installing a header. If this setting is done, care must be taken to
disconnect or remove the onboard flash device, as this device is a 1.8 V only device.
This configuration is selected to demonstrate the 3.3 V capability and to allow for demonstration of a high-speed
low-power (1.8 V) QSPI flash device.
Table 11 describes the typical power supply configurations for DCDC operation, while Table 12 describes the
typical power supply configurations for LDO operation.
MCX-N9XX-EVK power supply configurations for DCDC operation
Description JP38 JP27 JP35 JP18 JP36 JP31 JP37 JP47 JP15 JP45
Single supply
operation, IO
@ 3.3 V
1-2 1-2 1-2 2-3 1-2 1-2 1-2 1-2 1-2 1-2
Single supply
operation, IO
@ 1.8 V
2-3 1-2 1-2 2-3 2-3 Open 2-3 2-3 2-3 2-3
Dual IO, 3.3 V
and 1.8 V
1-2 1-2 1-2 2-3 2-3 2-3 1-2
or
2-3
1-2
or
2-3
1-2
or
2-3
1-2
or
2-3
Table 11. Power supply configurations for DCDC operation
MCX-N9XX-EVK power supply configurations for LDO operation
Description JP38 JP27 JP35 JP18 JP36 JP31 JP37 JP47 JP15 JP45
Single supply
operation, IO
@ 3.3 V
1-2 3-4
5-6
Open 1-2 1-2 1-2 1-2 1-2 1-2 1-2
Single supply
operation, IO
@ 1.8 V
2-3 3-4
5-6
Open 1-2 2-3 Open 2-3 2-3 2-3 2-3
Dual IO, 3.3 V
and 1.8 V
1-2 3-4
5-6
Open 1-2 1-2 2-3 1-2
or
2-3
1-2
or
2-3
1-2
or
2-3
1-2
or
2-3
Table 12. Power supply configurations for LDO operation
2.1.2 DC-DC inductor
The MCX-N9XX-EVK board uses a 1.5 μH DC-DC inductor L1 (Taiyo Yuden LSBHB2520MKT1R5M). The
inductor is enabled when the board is configured in DC-DC Buck mode. Figure 12 shows the DC-DC inductor
circuit diagram of the MCX-N9XX-EVK board.
UM12036 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.
User manual Rev. 1 — 20 January 2024
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