Quectel RM500Q-AE - Page 51

5G Module Series
RM500Q-AE&RM502Q-AE Hardware Design
RM500Q-AE&RM502Q-AE_Hardware_Design 51 / 83
The following figure shows a reference circuit of these four pins.
Host Module
CONFIG_0
CONFIG_1
CONFIG_2
CONFIG_3
GPIO
GPIO
GPIO
GPIO
21
69
75
1
VCC_IO_HOST
R1
10k
R2
10k
R3
10k
R4
10k
NM-0Ω
NM-0Ω
NM-0Ω
0Ω
Note: The voltage level of VCC_IO_HOST depends on the host side and could be 1.8 V or 3.3 V.
Figure 25: Recommended Circuit of Configuration Pins
Table 222221: Configuration Pins List of M.2 Specification
69
CONFIG_1
DO
0
Connected to GND internally
75
CONFIG_2
DO
0
Not connected internally
1
CONFIG_3
DO
0
Not connected internally
Config_0
(Pin 21)
Config_1
(Pin 69)
Config_2
(Pin 75)
Config_3
(Pin 1)
Module Type and
Main Host Interface
Port
Configuration
NC
GND
NC
NC
Quectel defined
N/A