Quectel RM500Q-GL

5G Module Series
RM500Q-GL Hardware Design
RM500Q-GL_Hardware_Design 21 / 85
26
W_DISABLE2#
DI, OD
GNSS disable control.
Active LOW
1.8/3.3 V
27
GND
Ground
28
PCM_SYNC
DIO, PD
PCM data frame sync
1.8 V
29
USB_SS_TX_M
AO
USB 3.1 super-speed
transmit (-)
30
USIM1_RST
DO, PD
(U)SIM1 card reset
USIM1_VDD
1.8/3.0 V
31
USB_SS_TX_P
AO
USB 3.1 super-speed
transmit (+)
32
USIM1_CLK
DO, PD
(U)SIM1 card clock
USIM1_VDD
1.8/3.0 V
33
GND
Ground
34
USIM1_DATA
DIO, PU
(U)SIM1 card data
USIM1_VDD
1.8/3.0 V
35
USB_SS_RX_M
AI
USB 3.1 super-speed
receive (-)
36
USIM1_VDD
PO
Power supply for
(U)SIM1 card
USIM1_VDD
1.8/3.0 V
37
USB_SS_RX_P
AI
USB 3.1 super-speed
receive (+)
38
SDX2AP_STATUS*
DO, PD
Status indication to AP
1.8 V
39
GND
Ground
40
USIM2_DET
1)
DI, PU
(U)SIM2 card insertion
detection
1.8 V
41
PCIE_TX_M
AO
PCIe transmit (-)
42
USIM2_DATA
DIO, PU
(U)SIM2 card data
USIM2_VDD
1.8/3.0 V
43
PCIE_TX_P
AO
PCIe transmit (+)
44
USIM2_CLK
DO, PD
(U)SIM2 card clock
USIM2_VDD
1.8/3.0 V
45
GND
Ground
46
USIM2_RST
DO, PD
(U)SIM2 card reset
USIM2_VDD
1.8/3.0 V
47
PCIE_RX_M
AI
PCIe receive (-)
48
USIM2_VDD
PO
Power supply for
USIM2_VDD