5G Module Series
RM500Q-GL Hardware Design
RM500Q-GL_Hardware_Design 42 / 85
should pay attention to the selection of the device. Typically, the stray capacitance should be less
than 1.0 pF for USB 2.0, and less than 0.15 pF for USB 3.1.
⚫ Keep the ESD protection devices as close to the USB connector as possible.
⚫ If possible, reserve 0 Ω resistors on USB_DP and USB_DM lines respectively.
4.3. PCIe Interface
RM500Q-GL provides one integrated PCIe (Peripheral Component Interconnect Express) interface.
⚫ PCI Express Base Specification Revision 3.0 compliant
⚫ Data rate up to 8 Gbps per lane
4.3.1. PCIe Operating Mode
RM500Q-GL supports endpoint (EP) mode and root complex (RC) mode. In EP mode, the module is
configured as a PCIe EP device. In RC mode, the module is configured as a PCIe root complex.
AT+QCFG="pcie/mode" is used to set PCIe RC/EP mode.
Parameter
Response
If the optional parameter is omitted, query the current setting:
+QCFG: "pcie/mode",<mode>
OK
If the optional parameter is specified, set PCIe RC/EP mode:
OK
If there is any error:
ERROR
The command takes effect after the module is restarted.
The configuration will be saved automatically.
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