Renesas RZ/T2M

Renesas Starter Kit+ for RZ/T2M 6. Configuration
R20UT4939EG0100 Rev. 1.00 Page 49 of 87
Apr 20, 2022
6.11 Ethernet Configuration
Table 6-31, Table 6-32, Table 6-33 below details the function of the option links associated with Ethernet
Configuration.
Table 6-31: Ethernet Configuration Option Links (1)
Signal name
MPU
MPU Peripheral Selection
Destination Selection
Pin
Port
Signal Fit DNF
Interface
/Function
Fit DNF
ETH0_TXCLK
R9
P09_7
ETH0_TXCLK
R103
-
IC35.37
-
-
ETH0_TXEN
W7
P10_0
ETH0_TXEN
R104
-
IC35.33
-
-
ETH0_TXD0
Y6
P09_6
ETH0_TXD0
R102
-
IC35.38
-
-
ETH0_TXD1
T9
P09_5
ETH0_TXD1
R101
-
IC35.40
-
-
ETH0_TXD2
R8
P09_4
ETH0_TXD2
R100
-
IC35.41
-
-
ETH0_TXD3
W6
P09_3
ETH0_TXD3
R99
-
IC35.42
-
-
ETH0_RXCLK
V7
P08_6
ETH0_RXCLK
-
-
IC35.32
R228
-
ETH0_RXDV
Y3
P08_5
ETH0_RXDV
-
-
IC35.30
R229
-
ETH0_RXD0
Y7
P10_1
ETH0_RXD0
-
-
IC35.29
R230
-
ETH0_RXD1
V8
P10_2
ETH0_RXD1
-
-
IC35.27
R231
-
ETH0_RXD2
V9
P10_3
ETH0_RXD2
-
-
IC35.26
R232
-
ETH0_RXD3
W4
P08_4
ETH0_RXD3
-
-
IC35.25
R233
-
ETH0_REFCLK
T8
P09_1
ETH0_REFCLK
R98
-
IC34.2
R227
-
ETH0_REFCLK_25 - -
ETH0_REFCLK
R227
R226
IC35.63 R243 -
ETH0_REFCLK_G*
1
R226, R161
R227
*
1
: In the default RSK+ configuration, ETH0_REFCLK_G signal is not connected to the XTAL1 pin of the
Ethernet controller IC (IC35). If you want to connect the external clock (X1) on the RSK+ to the Ethernet
controller IC, configure as shown in Table 6-31 above.
Table 6-32: Ethernet Configuration Option Links (2)
Signal name
MPU
MPU Peripheral Selection
Destination Selection
Pin
Port
Signal Fit DNF
Interface
/Function
Fit DNF
ETH1_TXCLK
U1
P06_4
ETH1_TXCLK
R96
-
IC31.37
-
-
ETH1_TXEN
T3
P06_5
ETH1_TXEN
R97
-
IC31.33
-
-
ETH1_TXD0
P5
P06_3
ETH1_TXD0
R95
-
IC31.38
-
-
ETH1_TXD1
T2
P06_2
ETH1_TXD1
R94
-
IC31.40
-
-
ETH1_TXD2
P6
P05_7
ETH1_TXD2
R90
-
IC31.41
-
-
ETH1_TXD3
T1
P06_0
ETH1_TXD3
R92
-
IC31.42
-
-
ETH1_RXCLK
U3
P07_3
ETH1_RXCLK
-
-
IC31.32
R205
-
ETH1_RXDV
W1
P07_2
ETH1_RXDV
-
-
IC31.30
R206
-
ETH1_RXD0
U2
P06_6
ETH1_RXD0
-
-
IC31.29
R207
-
ETH1_RXD1
V1
P06_7
ETH1_RXD1
-
-
IC31.27
R208
-
ETH1_RXD2
V2
P07_0
ETH1_RXD2
-
-
IC31.26
R209
-
ETH1_RXD3
R5
P07_1
ETH1_RXD3
-
-
IC31.25
R210
-
ETH1_REFCLK
R3
P06_1
ETH1_REFCLK
R93
-
IC30.2
R204
-
ETH1_REFCLK_25 - -
ETH1_REFCLK
R204
R203
IC31.63 R220 -
ETH1_REFCLK_G*
1
R203, R162
R204
*
1
: In the default RSK+ configuration, ETH1_REFCLK_G signal is not connected to the XTAL1 pin of the
Ethernet controller IC (IC31). If you want to connect the external clock (X1) on the RSK+ to the Ethernet
controller IC, configure as shown in Table 6-32 above.