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Renesas RZ/T2M

Renesas RZ/T2M
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Renesas Starter Kit+ for RZ/T2M 5. User Circuitry
R20UT4939EG0100 Rev. 1.00 Page 25 of 87
Apr 20, 2022
5.12 Ethernet
When running any Ethernet software, a unique MAC address should be used. A unique Renesas allocated MAC
address is attached to the PCB as a sticker and should always be used with this device to ensure full compatibility
when using other Renesas hardware on a common Ethernet connection.
Three Ethernet PHY ICs are fitted to the CPU board and are connected to the MPU Ethernet peripherals. The
RZ/T2M MPU supports half and full duplex, 10Mb/s and 100Mb/s and 1000Mb/s transmission and reception.
Refer to section 5.4 Ethernet LEDs. The connections for the Ethernet controller are listed in Table 5-15, Table
5-16, Table 5-17, Table 5-18, Table 5-19 below.
Note that Ethernet port 2 cannot be used at the same time as SDRAM.
Table 5-15: Ethernet Connections (ETH0)
Ethernet signal Function
MPU
Port
Pin
ETH0_TXCLK
RGMII: Transmit clock output
P09_7
R9
ETH0_TXEN
RGMII: Transmit data enable / Transmit data error
P10_0
W7
ETH0_TXD0
RGMII: Transmit data0
P09_6
Y6
ETH0_TXD1
RGMII: Transmit data1
P09_5
T9
ETH0_TXD2
RGMII: Transmit data2
P09_4
R8
ETH0_TXD3
RGMII: Transmit data3
P09_3
W6
ETH0_RXCLK
RGMII: Receive clock input
P08_6
V7
ETH0_RXDV
RGMII: Receive data valid / Receive data error
P08_5
Y3
ETH0_RXD0
RGMII: Receive data0
P10_1
Y7
ETH0_RXD1
RGMII: Receive data1
P10_2
V8
ETH0_RXD2
RGMII: Receive data2
P10_3
V9
ETH0_RXD3
RGMII: Receive data3
P08_4
W4
ETH0_REFCLK
Outputs 25MHz clock for EtherPHY0
P09_1
T8
Table 5-16: Ethernet Connections (ETH1)
Ethernet signal Function
MPU
Port
Pin
ETH1_TXCLK
RGMII: Transmit clock output
P06_4
U1
ETH1_TXEN
RGMII: Transmit data enable / Transmit data error
P06_5
T3
ETH1_TXD0
RGMII: Transmit data0
P06_3
P5
ETH1_TXD1
RGMII: Transmit data1
P06_2
T2
ETH1_TXD2
RGMII: Transmit data2
P05_7
P6
ETH1_TXD3
RGMII: Transmit data3
P06_0
T1
ETH1_RXCLK
RGMII: Receive clock input
P07_3
U3
ETH1_RXDV
RGMII: Receive data valid / Receive data error
P07_2
W1
ETH1_RXD0
RGMII: Receive data0
P06_6
U2
ETH1_RXD1
RGMII: Receive data1
P06_7
V1
ETH1_RXD2
RGMII: Receive data2
P07_0
V2
ETH1_RXD3
RGMII: Receive data3
P07_1
R5
ETH1_REFCLK
Outputs 25MHz clock for EtherPHY1
P06_1
R3

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