Rohde & Schwarz M3SR Series 4100 - Fig. 1.4 Synthesizer, Block Diagram

R&S M3SR Series 4100 HF Transceivers Synthesizer - Function
6124.9007.82.01 1.12
Fig. 1.4 Synthesizer, Block Diagram
VCXO
80 MHzADF4001 5 Hz 90 MHz 10 dB
10 .. 12 MHz
= 2*(5..6 MHz)
50 kHz
VCO
DDS
5 .. 6 MHz
8 MHz 8 MHz
95 MHz
80 MHz
85 .. 86 MHz
15 MHz
PLL
ADF4001
3 kHz
VCO
VCO
VCO
VCO
ATTEN
40 .. 46 MHz
46 .. 53 MHz
53 .. 60 MHz
60 .. 70 MHz
ATTEN
10 dB
A
D
Pretune
L
O
L
O
40.048
...
70.048 M
H
(0 dBm)
Cleaning Loop
LO2 Loop
LO1 Loop
80 MHz
(0 dBm)
Control
FPGA
Parallel
RCB-Interface
PLL Mainloop
VCO Control
Pretune
DDS Cleaning Loop
PLL Cleaning Loop
PLL Reference Loop
RCB
ADF4001AD9851
R
N
R
N
R
N
LO2_LEV
(to BIT ADC)
180 pin
Connector
X102
X101
Comp.
10 MHz
Flash
10K_REF
(3.3V CMOS)
10 kHz
100K_REF
(100 kHz sinewave 1V
eff
)
X21
X22
X23
A
D
10 MHz Loop
A
D
7 Hz
CPLD
Cleaning Loop
PLL
10 kHz
Divider
100 kHz
Divider
10M_REF
(sinewave)
1 / 5 / 10 MHz (0dBm)
Comp.
100 kHz
100 kHz
AD7476
AD5310
A
D
AD5310
(not fitted)
Ref.
AD5310
AD7476
TLV2548IPW
BIT ADC
LO1_LEV
(to BIT ADC)
LO2_TUNE
(to BIT ADC)
CLEAN_LOOP_TUNE
(to BIT ADC)
ATTEN
LO2 Loop
LO1 Loop
A
D
A
D
MUX Control
3
Temperature
8:1
MUX
8
Vcc
8:1
MUX
8
Vcc
1
from LO1 Loop
from Clean. Loop
from LO2 Loop
8
1
1
1
1
2
12 bit
10 bit
12 bit
12 bit
JTAG
to FPGA
and CPLD
X103
LEDLED LED
Error
Warning
Go
LO1_LOCK
(to FPGA)
CLEAN_LOCK
(to FPGA)
PLL
LO2_LOCK
(to FPGA)
PLL
OVEN_COLD
(to FPGA)
OCXO
10 MHz
(sinewave)
ICN-S4100-A-E11100-R-D0894-00202-A-01-1