Sanyo PLC-XF1000 - Page 77

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Electrical Adjustment
GROUP NO. ITEM FUNCTION RANGE INITIAL VALUE NOTE
37 WXGA6 (r26) 0 ~ 255 32
38 WXGA7 (r26) 0 ~ 255 32
39 WXGA8 (r26) 0 ~ 255 32
40 WXGA9 (r26) 0 ~ 255 32
41 WXGA10 (r26) 0 ~ 255 32
42 SXGA1 (r26) 0 ~ 255 32
43 SXGA2 (r26) 0 ~ 255 32
44 SXGA3 (r26) 0 ~ 255 32
45 SXGA4 (r26) 0 ~ 255 32
46 SXGA5 (r26) 0 ~ 255 32
47 SXGA6 (r26) 0 ~ 255 32
48 SXGA7 (r26) 0 ~ 255 32
49 SXGA8 (r26) 0 ~ 255 32
50 SXGA9 (r26) 0 ~ 255 32
51 SXGA10 (r26) 0 ~ 255 32
52 SXGA11 (r26) 0 ~ 255 32
53 SXGA12 (r26) 0 ~ 255 32
54 SXGA13 (r26) 0 ~ 255 32
55 SXGA14 (r26) 0 ~ 255 32
56 SXGA15 (r26) 0 ~ 255 32
57 SXGA16 (r26) 0 ~ 255 32
58 SXGA17 (r26) 0 ~ 255 32
59 SXGA18 (r26) 0 ~ 255 32
60 SXGA19 (r26) 0 ~ 255 32
61 SXGA20 (r26) 0 ~ 255 32
62 SXGA21 (r26) 0 ~ 255 32
63 SXGA+1 (r26) 0 ~ 255 32
64 SXGA+2 (r26) 0 ~ 255 32
65 SXGA+3 (r26) 0 ~ 255 32
66 UXGA1 (r26) 0 ~ 255 32
67 UXGA2 (r26) 0 ~ 255 32
68 UXGA3 (r26) 0 ~ 255 32
69 UXGA4 (r26) 0 ~ 255 32
70 UXGA5 (r26) 0 ~ 255 32
71 MAC LC 13 (r26) 0 ~ 255 32
72 MAC II 13 (r26) 0 ~ 255 32
73 MAC II 16 (r26)) 0 ~ 255 32
74 MAC II 19 (r26) 0 ~ 255 32
75 MAC II 21 (r26) 0 ~ 255 32
76 MAC II A (r26) 0 ~ 255 32
77 MAC II B (r26) 0 ~ 255 32
78 1035i/60, 1080i/60 (r26) 0 ~ 255 32
79 1080i/50 (r26) 0 ~ 255 32
80 (r26) 0 ~ 255 32
81 575p (r26) 0 ~ 255 32
82 480p (r26) 0 ~ 255 32
83
NTSC, NTSC4.43, PAL, PAL-M, PAL-
N,SECAM, PAL-6 0, NTSC-50, 575i,
480i
(r26) 0 ~ 255 32
84 SXGA+4 (r26) 0 ~ 255 32
85 SXGA+5 (r26) 0 ~ 255 32
86 1080PSE30 (r26) 0 ~ 255 32
87 1080PSE25 (r26) 0 ~ 255 32
88 1080PSE24 (r26) 0 ~ 255 32
89 WXGA11 (r26) 0 ~ 255 32
90 WXGA+1 (r26) 0 ~ 255 32
91 WXGA+2 (r26) 0 ~ 255 32
92 WSXGA+1 (r26) 0 ~ 255 32
93 WUXGA1 (r26) 0 ~ 255 32
94 WUXGA2 (r26) 0 ~ 255 32
95 WXGA12 (r26) 0 ~ 255 32
96 Default (r26) 0 ~ 255 32
324 ILS51002 - MISC CTRL
0 FBC OUTPUT SOURCE 01b : FBC out Terminal Output 0 ~ 1 0
330 MOTHER FPGA
0 DELAY TIME [SLOT1] MTHE Setting Digital signal and Clock 40MHz Over -64 ~ 63 -18
1 DELAY TIME [SLOT1] MAIN Setting Digital signal and Clock 40MHz Over -64 ~ 63 -32
2 DELAY TIME [SLOT2] MTHE Setting Digital signal and Clock 40MHz Over -64 ~ 63 0
3 DELAY TIME [SLOT2] MAIN Setting Digital signal and Clock 40MHz Over -64 ~ 63 0
4 DELAY TIME [SLOT3] MTHE Setting Digital signal and Clock 40MHz Over -64 ~ 63 -9
5 DELAY TIME [SLOT3] MAIN Setting Digital signal and Clock 40MHz Over -64 ~ 63 -22
6 DELAY TIME [SLOT4] MTHE Setting Digital signal and Clock 40MHz Over -64 ~ 63 -15
7 DELAY TIME [SLOT4] MAIN Setting Digital signal and Clock 40MHz Over -64 ~ 63 -28
382 SW FPGA - SETTING
0 CNTDN VON 0 ~ 1 0
1 FB HS GATE ON 0 ~ 1 0
2 MANUAL COAST ST 0 ~ 255 4
3 MANUAL COAST ED 0 ~ 255 4
4 MANUAL ON 0 ~ 1 0