Sanyo PLC-XF1000 - Page 78

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Electrical Adjustment
GROUP NO. ITEM FUNCTION RANGE INITIAL VALUE NOTE
5 UVDLT 0 ~ 15 3
383 SW FPGA - VGATE
0 VAGTE REASET CNT 0 ~ 255 100
1 VAGTE WIDTH 0 ~ 255 12
2 VAGTE AND LINE 0 ~ 255 0
384 SW FPGA - COAST
0 COAST ON 0 ~ 1 0
385 SW FPGA - TEST
0 TEST HGATE 0 ~ 1 0
386 SW FPGA - Clamp Level r00 ~ r03
0 DAT_CLP_RLVLE 0 ~ 1023 16
1 DAT_CLP_GLVLE 0 ~ 1023 16
2 DAT_CLP_BLVLE 0 ~ 1023 16
387 SW FPGA - OFFSET r21 ~ r23
0 R_OFFSET 0 ~ 255 240
1 G_OFFSET 0 ~ 255 240
2 B_OFFSET 0 ~ 255 240
388 FPGA NIOS - Image RGB Table
0 IMAGE_RGB_TBL 0 ~ 7 0
400 SCART (480i) [DVI - Dsub Card]
0 Total Dots 0 ~ 3000 1292
1 Disp Dots 0 ~ 3000 1024
2 H Back Porch 0 ~ 3000 191
3 V Back Porch 0 ~ 3000 42
4 Disp Line 0 ~ 1500 468
8 VSBEG 0 ~ 15 2
9 Filed Enable 0 ~ 1 1
10 FLDBEG 0 ~ 15 7
11 FLDEND 0 ~ 15 13
401 SCART (575i) [DVI - Dsub Card]
0 Total Dots 0 ~ 3000 1322
1 Disp Dots 0 ~ 3000 1024
2 H Back Porch 0 ~ 3000 220
3 V Back Porch 0 ~ 3000 57
4 Disp Line 0 ~ 1500 552
8 VSBEG 0 ~ 15 2
9 Filed Enable 0 ~ 1 1
10 FLDBEG 0 ~ 15 7
11 FLDEND 0 ~ 15 13
410 RGB Video (480i) [DVI - Dsub Card]
0 Total Dots 0 ~ 3000 1292
1 Disp Dots 0 ~ 3000 1024
2 H Back Porch 0 ~ 3000 190
3 V Back Porch 0 ~ 3000 42
4 Disp Line 0 ~ 1500 468
8 VSBEG 0 ~ 15 1
9 Filed Enable 0 ~ 1 1
10 FLDBEG 0 ~ 15 1
11 FLDEND 0 ~ 15 9
411 RGB Video (575i) [DVI - Dsub Card]
0 Total Dots 0 ~ 3000 1322
1 Disp Dots 0 ~ 3000 1024
2 H Back Porch 0 ~ 3000 217
3 V Back Porch 0 ~ 3000 56
4 Disp Line 0 ~ 1500 552
8 VSBEG 0 ~ 15 1
9 Filed Enable 0 ~ 1 1
10 FLDBEG 0 ~ 15 1
11 FLDEND 0 ~ 15 9
412 RGB Video (480P) [DVI - Dsub Card]
0 Total Dots 0 ~ 3000 1245
1 Disp Dots 0 ~ 3000 1024
2 H Back Porch 0 ~ 3000 168
3 V Back Porch 0 ~ 3000 39
4 Disp Line 0 ~ 1500 476
8 VSBEG 0 ~ 15 2
9 Filed Enable 0 ~ 1 0
10 FLDBEG 0 ~ 15 0
11 FLDEND 0 ~ 15 0