Sanyo PLC-XP100L - Input & Signal Processing Stage

-65-
Chassis Description
DVI-D
PJ-Net
INPUT1
D_SUB15D_SUB15
INPUT2
BNC
13 11
89 90
1
53,54
140 141 129
85 81 83
1,3,5
8,10,12
1,3,5
13,3 12.5
5 6 2 7
4 42
2
110 111
6 7
30
258 179 336
21 15
8 3
109
1
7
114 113 112
23
1
13 22
15,17
RCAS-VIDEO
INPUT3MONITOR
OUT
C
CV/Y
CR CB
Y
SCART_R
OUT_R/CR
OUT_G/Y
OUT_B/CB
OUT_HS
OUT_VS
OUT_SW
SCART_G
SCART_B
S_C
Y_IN
CB_IN CR_IN
S_Y
SCART_CV
S_C
S_Y
Y_IN
-IN1/IN2
IN1_HSYNC
IN1_VSYNC
IN1_CLK
IC1012 IC1013
IC102
IC9203
Q106
IC2001
BNC/RCA-SW
<AD8183>
IC1001
IN1/IN2-SW
<AD8183>
IC1002
SYNC-SW
<TC40537>
IC4001
BUFFER-SW
<AD8075>
IC4002
BUFFER-SW
IC9201
VIDEO
DECODER
&
AV A/D
<CXD3815>
IC9202
SDRAM
IC101
VIDEO
SELECTOR
<CXA2239>
IN1UV[0-9] IN1Y[0-9]
RGB
HV HV
RGB
Y,CR,CB
AV
MAIN
K21A K10A
RGB
Q4001
HV
IC301
<PW388>
SCALER
8,10,12
10,12,14
3,6
IC1011
SYNC
SEP.
<BA7078>
IN2:H
-BNC/RCA
RCA:H
OUT:H
-IN1/IN2
IN1:H
113 112 4
88
20
22
#IN1/IN2
Y:H
5
1
3
22
7 5 3
1 1
7
5 2
9,11
14 20 18 16 4
18 16
14
12
10
87
64 70
268
90 89
78 77
59
5 3 7
IN0_HSYNC
IN0_VSYNC
IN0_CLK
CG_HSYNC
CG_VSYNC
85
124
CG_CLK
IC1201
FPGA
<XC3S50>
IC8201
PC A/D
<AD9882>
IN0BE[2-7] IN0GE[0-7] IN0RE[0-7]
CG_B[0-7] CG_G[0-7] CG_R[0-7]
R
G
B
R_IN
G_IN
B_IN
80
VSOUT
79
HSOUTHS
VS
OUT_HS
OUT_VS
7 3
5 2
IC8202 IC8203
Y_IN
CB_IN CR_IN
Y_IN
CB_IN CR_IN
SCART_CV
IC1006
25
111
|
120
21 17 33 29 57 53 49 41 45 37
Input & signal processing stage