Instruction List
B-4
ET 200S Interface Module IM 151/CPU
A5E00058783-01
Address Registers AR1 and AR2 (32 Bits)
The address registers contain the area-specific or general addresses for
instructions that use register-indirect addressing. The address registers are 32 bits
long.
The area-internal and/or area-crossing addresses have the following structure:
Area-internal address:
00000000 00000bbb bbbbbbbb bbbbbxxx
Area-crossing address:
10000yyy 00000bbb bbbbbbbb bbbbbxxx
Legend: b Byte address
x Bit number
y Area identifier (see Appendix B.4)
Status Word (16 Bits)
The status word bits are evaluated or set by the instructions.
The status word is 16 bits long.
Bit Assign-
ment
Description
0 /FC First check bit *
1 RLO Result of (previous) logic operation
2 STA Status *
3 OR Or *
4 OS Stored overflow
5 OV Overflow
6 A0 Condition code
7 A1 Condition code
8 BR Binary result
9 ...
15
Unassigned –
* Bit cannot be evaluated in the user program with the L STW instruction,
since it is not updated at program runtime.
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