Siemens SIMATIC IM 151/CPU - Bit Logic Instructions

Instruction List
B-13
ET 200S Interface Module IM 151/CPU
A5E00058783-01
B.6 Bit Logic Instructions
Examination of the signal state of the addressed instruction and gating of the result
with the RLO in accordance with the appropriate logic function.
Instru- Length Typical Execution Time in s
ction
Address ID Description
g
in
Words
Direct Addres-
sing
Indirect Ad-
dressing
*
A
I/O
M
L
DBX/DIX
AND
Input/output
Memory markers
Local data bit
Data bit
1**/2
1**/2
2
2
0.3
0.6
0.9
2.8
1.6+
1.7+
1.8+
2.5+
[AR1,m]
[AR2,m]
Parameters
I/Q/M/L/DBX/DIX (addressed
(area-crossing) via AR1/AR2 or
via parameter)
2 –
–
–
+
+
+
AN
I/O
M
L
DBX/DIX
AND NOT
Input/output
Memory markers
Local data bit
Data bit
2 0.5
0.8
1.0
3.1
1.9+
2.1+
2.2+
2.8+
[AR1,m]
[AR2,m]
Parameters
I/Q/M/L/DBX/DIX (addressed
(area-crossing) via AR1/AR2 or
via parameter)
2 –
–
–
–
–
–
Status word for: A, AN BR A1 A0 OV OS OR STA RLO /FC
Instruction depends on: – – – – – Yes – Yes Yes
Instruction controls: – – – – – Yes Yes Yes 1
O
I/O
M
L
DBX/DIX
OR
Input/output
Memory markers
Local data bit
Data bit
1**/2
1**/2
2
2
0.3
0.7
0.9
2.9
1.6+
1.7+
1.8+
2.5+
[AR1,m]
[AR2,m]
Parameters
I/Q/M/L/DBX/DIX (addressed
(area-crossing) via AR1/AR2 or via
parameter)
2 –
–
–
+
+
+
ON
I/O
M
L
DBX/DIX
OR NOT
Input/output
Memory markers
Local data bit
Data bit
1**/2
1**/2
2
2
0.5
0.8
2.0
3.1
1.6+
2.0+
2.2+
2.8+
[AR1,m]
[AR2,m]
Parameters
I/Q/M/L/DBX/DIX (addressed
(area-crossing) via AR1/AR2 or via
parameter)
2 –
–
–
+
+
+
Status word for: O, ON BR A1 A0 OV OS OR STA RLO /FC
Instruction depends on: – – – – – – – Yes Yes
Instruction controls: – – – – – 0 Yes Yes 1
* + time for loading the address of the instruction
** With direct instruction addressing