Instruction List
B-19
ET 200S Interface Module IM 151/CPU
A5E00058783-01
B.11 Logic Instructions with Condition Code Bits
Examination of the signal state of the specified conditions and gating of the result
with the RLO in accordance with the appropriate logic function.
In-
struc-
tion
Address
ID
Description
Length
in
Words
Typical Execution
Time in s
A ==0 AND result=0
(CC 1=0) and (CC 0=0)
1 0.6
>0 AND result>0
(CC 1=1) and (CC 0=0)
1 0.9
<0 AND result<0
(CC 1=0) and (CC 0=1)
1 0.9
<>0 AND result0
((CC 1=0) and (CC 0=1) or (CC 1=1) and (CC
0=0))
1 0.6
<=0 AND result<=0
((CC 1=0) and (CC 0=1) or (CC 1=0) and (CC
0=0))
1 0.6
>=0 AND result>=0
((CC 1=1) and (CC 0=0) or (CC 1=0) and (CC
0=0))
1 0.6
AO AND unordered
(CC 1=1) and (CC 0=1)
1 0.6
OS AND OS=1 1 0.3
BR AND BR=1 1 0.3
OV AND OV=1 1 0.3
Status word for: A condition BR A1 A0 OV OS OR STA RLO /FC
Instruction depends on: Yes Yes Yes Yes Yes Yes – Yes Yes
Instruction controls: – – – –- – Yes Yes Yes 1