Figure 11.4. Power Plane (Layer 4)
The following figure shows Layer 5, which is the power plane with the power routed to the clock output power pins.
Figure 11.5. Layer 5 Power Routing on Power Plane (Layer 5)
The following figure is another ground plane similar to Layer 3.
Si5341, Si5340 Rev D Family Reference Manual • Crystal and Device Circuit Layout Recommendations
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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