Figure 11.14. Low-Speed CMOS Control and Status Signal Layer 6 (Bottom Layer)
For any high-speed, low-jitter application, the clock signal runs should be impedance-controlled to 100 Ω differential or 50 Ω single-
ended. Differential signaling is preferred because of its increased immunity to common-mode noise. All clock I/O runs should be
properly terminated.
Si5341, Si5340 Rev D Family Reference Manual • Crystal and Device Circuit Layout Recommendations
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