Skyworks Si5341 - Page 89

Reg Address Bit Field Type Setting Name Description
0x0021 2:1 R/W IN_SEL Selects the reference clock input to the PLL when
IN_SEL_REGCTRL=1.
0 IN0
1 IN1
2 IN2
3 XA/XB
Table 14.111. 0x002B SPI 3 vs 4 Wire
Reg Address Bit Field Type Setting Name Description
0x002B 3 R/W SPI_3WIRE 0 for 4-wire SPI, 1 for 3-wire SPI
Table 14.112. 0x002C LOS Enable
Reg Address Bit Field Type Setting Name Description
0x002C 3:0 R/W LOS_EN 1 to enable LOS for a clock input;
0 for disable
0x002C 4 R/W LOSXAXB_DIS 0 to enable LOS for the XAXB input
1 to disable the LOS for the XAXB input
• Input 0 (IN0): LOS_EN[0]
• Input 1 (IN1): LOS_EN[1]
• Input 2 (IN2): LOS_EN[2]
• FB_IN: LOS_EN[3]
Table 14.113. 0x002D Loss of Signal Time Value
Reg Address Bit Field Type Setting Name Description
0x002D 1:0 R/W LOS0_VAL_TIME Clock Input 0
0 for 2 msec
1 for 100 msec
2 for 200 msec
3 for one second
0x002D 3:2 R/W LOS1_VAL_TIME Clock Input 1, same as above
0x002D 5:4 R/W LOS2_VAL_TIME Clock Input 2, same as above
0x002D 7:6 R/W LOS3_VAL_TIME Clock Input 3, same as above
When an input clock is gone (and therefore has an active LOS alarm), if the clock returns, there is a period of time that the clock must
be within the acceptable range before the alarm is removed. This is the LOS_VAL_TIME.
Si5341, Si5340 Rev D Family Reference Manual • Register Map
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