Table 14.120. 0x003A-0x003B LOS2 Clear Threshold
Reg Address Bit Field Type Setting Name Description
0x003A 7:0 R/W LOS2_CLR_THR 16-bit Threshold Value
0x003B 15:8 R/W LOS2_CLR_THR
ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 2, given a particular frequency plan.
Table 14.121. 0x003C-0x003D LOS3 Clear Threshold
Reg Address Bit Field Type Setting Name Description
0x003C 7:0 R/W LOS3_CLR_THR 16-bit Threshold Value
0x003D 15:8 R/W LOS3_CLR_THR
ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 3, given a particular frequency plan.
Table 14.122. 0x0041-0x0044 LOS Pre-Divider for IN0, IN1, IN3, FB_IN
Reg Address Bit Field Type Setting Name Description
0x0041 4:0 R/W LOS0_DIV_SEL A pre-divider that is configured by ClockBuilder Pro
0x0042 4:0 R/W LOS1_DIV_SEL A pre-divider that is configured by ClockBuilder Pro
0x0043 4:0 R/W LOS2_DIV_SEL A pre-divider that is configured by ClockBuilder Pro
0x0044 4:0 R/W LOS3_DIV_SEL A pre-divider that is configured by ClockBuilder Pro
The following are the pre-divider values for the above-listed registers values.
Si5341, Si5340 Rev D Family Reference Manual • Register Map
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