Sony HCD-EA20 - Page 72

72
HCD-EA20
Pin No.
201
202
203
204
205
206
207
208
I/O
I
I
I/O
—
—
I/O
I/O
—
Pin Name
TCK
RESET
BUS CLK
GND
VDD
HA3
HA2
GNDP
Description
TCK signal input
ZIVA reset input
Not used
Ground terminal (inside core)
Power supply terminal (+1.8V) (inside core)
Address bus 3
Address bus 2
Ground terminal (I/O signal)
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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