Sony HCD-SHAKEX3 - Page 58

HCD-SHAKEX1/SHAKEX3/SHAKEX7
58
IC106 MX25L3235EM2I-10G (MOTHERBOARD BOARD (8/8))
IC302 MX25L3235EM2I-10G (MOTHERBOARD BOARD (3/8))
IC305 BU33TD3WG-TR (MOTHERBOARD BOARD (3/8))
CS
SO/SIO1
WP/SIO2
GND
4
SI/SIO0
SCLK
VCC
8
HOLD/SIO3
Data
Register
SRAM
Buffer
Sense
Amplifier
Output
Buffer
Address
Generator
Mode
Logic
Clock Generator
Y-Decoder
State
Machine
HV
Generator
Memory Array
Page Buffer
X-Decoder
1
3
6
7
5
2
+
–
VDD
1
GND
2
CE
3
VREF
OCP
TSD
STBY
Discharge
5VOUT
4NC
IC306 M12L64164A-7TG2Y (MOTHERBOARD BOARD (3/8))
Clock
Generator
Address
Command Decoder
Control Logic
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Bank A
Bank B
Bank C
Bank D
Sense Amplifier
Row Decoder
Column Decoder
Data Control Circuit
Latch Circuit
Input & Output
Buffer
NC
40
UDQM
39
CLK
38
CLKE
37
NC
36
A11
35
A9
34
A8
33
A7
32
A6
31
A5
30
A4
29
VSS
28
VDD
27
VSS
41
DQ8
42
VDDQ
43
DQ9
44
DQ10
45
VSSQ
46
DQ11
47
DQ12
48
VDDQ
49
DQ13
50
DQ14
51
VSSQ
52
DQ15
53
VSS
54
A3
26
A2
25
A1
24
A0
23
A10/AP
22
BA1
21
BA0
20
CS
19
RAS
18
CAS
17
WE
16
LDQM
15
VDD
14
1
VDD
2
DQ0
3
VDDQ
4
DQ1
5
DQ2
6
VSSQ
7
DQ3
8
DQ4
9
VDDQ
10
DQ5
11
DQ6
12
VSSQ
13
DQ7
Ver. 1.3