Sony MVC-FD81 - Camera;Fdd Interface Block Diagram

MVC-FD81
3-2. CAMERA/FDD INTERFACE BLOCK DIAGRAM
3-5 3-6 3-7 3-8
IC431 1,3
9.5Vp-p
78µsec
IC431 2,4
9.5Vp-p
78µsec
IC431 8
1.8Vp-p
78µsec
IC431 !∞,!§
4.5Vp-p
60nsec
IC431 !¢
4Vp-p
60nsec
IC101 2 – !¡
CAMERA REC/PB
3.1Vp-p
60nsec
IC101 !§
CAMERA REC/PB
60nsec
4.0Vp-p
IC101 @§ CAMERA REC
1.8Vp-p
78µsec
IC103 #§,$∞
CAMERA REC/PB
3.8Vp-p
60nsec
IC102 4
CAMERA REC/PB
3.8Vp-p
30nsec
IC102 @∞
CAMERA REC/PB
4.0Vp-p
60nsec
IC601 5
3.8Vp-p
60nsec
IC601 !¢
0.1Vp-p
78µsec
IC601 @£
0.18Vp-p
78nsec
IC601 !ª
0.16Vp-p
78µsec
IC601 #¶
3.8Vp-p
60nsec
IC801 *£
5.0Vp-p
16.26MHz
IC851 *º
7.41MHz
1.8Vp-p
IC601 $™
CAMERA REC/PB
3.2Vp-p
4.0MHz
6.875MHz