Sony STR-DA333ES - Page 39

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I/O
I
O
O
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—
I
O
—
O
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O
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O
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I
O
O
O
I
O
I/O
I/O
I/O
I/O
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I/O
I/O
O
—
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I
—
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O
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O
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O
Description
RF demodulator error or signal input
RF demodulator/DIR reset
Woofer gain control 6
Woofer gain control 12
Rear gain control 3
Rear gain control 6
Rear gain control 12
Power supply +5 V
UART input. Used for rewriting flash memory
UART output. Used for rewriting flash memory
Not used (Connected to ground)
Test pin
Surround mute in
Analog/digital selection (SN74HC157)
To CS4923 data input
To CS4923 clock
To CS4923 chip select
To CS4923 SPI data output
To CS4923 interrupt request
To CS4923 reset
To CXD2712 HCIF data write
To CXD2712 HCIF data read
To CXD2712 HCIF ready
To CXD2712 HCIF chip select
To CXD2712 HCIF data input/output
To CXD2712 HCIF data input/output
To CXD2712 HCIF data input/output
To CXD2712 HCIF data input/output
To CXD2712 HCIF data input/output
To CXD2712 HCIF data input/output
To CXD2712 HCIF data input/output
To CXD2712 HD 7
Ground
External power regulator capacitor 0.1 u is connected to this terminal
To CXD2712 HCIF address
To CXD2712 reset
To CXD2712 LFE detection
Digital power supply +5 V
Digital ground
DA AK4324 reset
DA AK4324 muting
Analog power supply +5 V
Power supply +5 V
Ground
Ground
AD AK5352 reset
Not used (Not connected, open)
To TC9299 strobe
To TC9299 data
To TC9299 clock
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
IC 1201 MB90574PFV-G-176-BND (DIGITAL BOARD)
Pin Name
RFERR
RERESET
SW6
SW12
REAR3
REAR6
REAR12
VCC
S1NI
SOT0
—
SIN1
SOT1
ANA/DIG
SCDIN
SCCLK
CS
SCDIO/OUT
INTREQ
RESET
XHDWR
XHDRD
HRDY
XHDCS
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
VSS
C
HA0
XRST
SOD
DVCC
DVSS
D/AINT
SMUTE
AVCC
AVR+
AVR-
AVSS
A/DINT
—
EVSTB
EVDATA
EVCLK