List of tables
Table 1. Document sections versus IEC 61508-2 Annex D safety requirements ...............................2
Table 2. SS1 and SS2 safe state details ..........................................................9
Table 3. CPU_SM_0....................................................................... 10
Table 4. CPU_SM_1....................................................................... 11
Table 5. CPU_SM_2....................................................................... 12
Table 6. CPU_SM_3....................................................................... 12
Table 7. CPU_SM_4....................................................................... 13
Table 8. CPU_SM_5....................................................................... 13
Table 9. CPU_SM_6....................................................................... 14
Table 10. CPU_SM_7....................................................................... 14
Table 11. CPU_SM_8....................................................................... 15
Table 12. MPU_SM_0 ...................................................................... 15
Table 13. MPU_SM_1 ...................................................................... 16
Table 14. BUS_SM_0 ....................................................................... 16
Table 15. BUS_SM_1 ....................................................................... 17
Table 16. RAM_SM_0 ...................................................................... 17
Table 17. RAM_SM_1 ...................................................................... 18
Table 18. RAM_SM_2 ...................................................................... 19
Table 19. RAM_SM_3 ...................................................................... 19
Table 20. RAM_SM_4 ...................................................................... 20
Table 21. RAM_SM_5 ...................................................................... 20
Table 22. RAM_SM_6 ...................................................................... 21
Table 23. FLASH_SM_0 ..................................................................... 21
Table 24. FLASH_SM_1 ..................................................................... 22
Table 25. FLASH_SM_2 ..................................................................... 22
Table 26. FLASH_SM_3 ..................................................................... 23
Table 27. FLASH_SM_4 ..................................................................... 23
Table 28. FLASH_SM_5 ..................................................................... 23
Table 29. FLASH_SM_6 ..................................................................... 24
Table 30. FLASH_SM_7 ..................................................................... 24
Table 31. FLASH_SM_8 ..................................................................... 25
Table 32. FLASH_SM_9 ..................................................................... 26
Table 33. FWR_SM_0 ...................................................................... 26
Table 34. VSUP_SM_0...................................................................... 26
Table 35. VSUP_SM_1...................................................................... 27
Table 36. VSUP_SM_2...................................................................... 27
Table 37. VSUP_SM_3...................................................................... 28
Table 38. VSUP_SM_4...................................................................... 28
Table 39. VSUP_SM_5...................................................................... 29
Table 40. CLK_SM_0 ....................................................................... 29
Table 41. CLK_SM_1 ....................................................................... 30
Table 42. CLK_SM_2 ....................................................................... 30
Table 43. CLK_SM_3 ....................................................................... 31
Table 44. GPIO_SM_0 ......................................................................31
Table 45. GPIO_SM_1 ......................................................................32
Table 46. GPIO_SM_2 ......................................................................32
Table 47. GPIO_SM_3 ......................................................................33
Table 48. DBG_SM_0....................................................................... 33
Table 49. LOCK_SM_0...................................................................... 33
Table 50. SYSCFG_SM_0 ................................................................... 34
Table 51. DIAG_SM_0 ...................................................................... 34
Table 52. DMA_SM_0 ...................................................................... 35
UM2305
List of tables
UM2305 - Rev 10
page 106/110
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