SM CODE MPU_SM_0
Detailed implementation
This method must be applied to MPU configuration registers (also unused by End
userApplication software).
Detailed information on the implementation of this method can be found in
Section 3.6.14 Extended interrupt and events controller (EXTI).
Error reporting Refer to NVIC_SM_0
Fault detection time Refer to NVIC_SM_0
Addressed fault model Refer to NVIC_SM_0
Dependency on Device configuration Refer to NVIC_SM_0
Initialization Refer to NVIC_SM_0
Periodicity Refer to NVIC_SM_0
Test for the diagnostic Refer to NVIC_SM_0
Multiple-fault protection Refer to NVIC_SM_0
Recommendations and known limitations Refer to NVIC_SM_0
Table 13. MPU_SM_1
SM CODE MPU_SM_1
Description MPU software test
Ownership End user
Detailed implementation
This method tests MPU capability to detect and report memory accesses violating the policy
enforcement implemented by the MPU itself.
The implementation is based on intentionally performing read and write accesses outside the
memory areas allowed by the MPU region programming, and collecting and verifying related
generated error exceptions.
Test can be executed with the final MPU region programming or with a dedicated one.
Error reporting Depends on implementation
Fault detection time Depends on implementation
Addressed fault model Permanent
Dependency on Device configuration None
Initialization Depends on implementation
Periodicity On demand
Test for the diagnostic Not applicable
Multiple-fault protection CPU_SM_0: Periodic core self-test software
Recommendations and known limitations
Startup execution of this safety mechanism is recommended for multiple fault mitigations -
refer to Section 4.1.3 Notes on multiple-fault scenario.
3.6.2 System bus architecture/BusMatrix
Table 14. BUS_SM_0
SM CODE BUS_SM_0
Description Periodic software test for interconnections
Ownership End user
UM2305
Hardware and software diagnostics
UM2305 - Rev 10
page 16/110
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