SM CODE CLK_SM_0
Dependency on Device configuration Refer to NVIC_SM_0
Initialization Refer to NVIC_SM_0
Periodicity Refer to NVIC_SM_0
Test for the diagnostic Refer to NVIC_SM_0
Multiple-fault protection Refer to NVIC_SM_0
Recommendations and known limitations Refer to NVIC_SM_0
Table 41. CLK_SM_1
SM CODE CLK_SM_1
Description Clock security system (CSS)
Ownership ST
Detailed implementation
The clock security system (CSS) detects the loss of high-speed external (HSE) oscillator clock
activity and executes the corresponding recovery action, such as:
• switch-off HSE
• commutation on the HIS
• generation of related NMI
Error reporting NMI
Fault detection time Depends on implementation (clock frequency value)
Addressed fault model Permanent/transient
Dependency on Device configuration None
Initialization CSS protection must be enabled through Clock interrupt register (RCC_CIR) after boot.
Periodicity Continuous
Test for the diagnostic CLK_SM_0: Periodic read-back of configuration registers
Multiple-fault protection CPU_SM_5: External watchdog
Recommendations and known limitations
It is recommended to carefully read reference manual instruction on NMI generation, in order
to correctly managing the faulty situation by Application software.
Table 42. CLK_SM_2
SM CODE CLK_SM_2
Description Independent watchdog
Ownership ST
Detailed implementation
The independent watchdog IWDG is able to detect failures in internal main MCU clock (lower
frequency).
Error reporting Reset signal generation
Fault detection time Depends on implementation (watchdog timeout interval)
Addressed fault model Permanent
Dependency on Device configuration None
Initialization
IWDG activation. It is recommended to use the hardware watchdog in Option byte settings
(IWDG is automatically enabled after reset).
Periodicity Continuous
Test for the diagnostic Refer to CPU_SM_6.
Multiple-fault protection CPU_SM_1: Control flow monitoring in Application software
UM2305
Hardware and software diagnostics
UM2305 - Rev 10
page 30/110
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